[llvm] c6d7e80 - [NFC][SROA] Ensure that all check lines in SROA tests are autogenerated
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 30 14:18:39 PST 2022
Author: Roman Lebedev
Date: 2022-12-01T01:18:23+03:00
New Revision: c6d7e80ec4c17a415673b1cfd25924f98ac83608
URL: https://github.com/llvm/llvm-project/commit/c6d7e80ec4c17a415673b1cfd25924f98ac83608
DIFF: https://github.com/llvm/llvm-project/commit/c6d7e80ec4c17a415673b1cfd25924f98ac83608.diff
LOG: [NFC][SROA] Ensure that all check lines in SROA tests are autogenerated
Added:
Modified:
llvm/test/Transforms/SROA/alignment.ll
llvm/test/Transforms/SROA/basictest.ll
llvm/test/Transforms/SROA/big-endian.ll
llvm/test/Transforms/SROA/dbg-addr-diamond.ll
llvm/test/Transforms/SROA/dbg-inline.ll
llvm/test/Transforms/SROA/dead-inst.ll
llvm/test/Transforms/SROA/fca.ll
llvm/test/Transforms/SROA/mem-par-metadata-sroa-cast.ll
llvm/test/Transforms/SROA/mem-par-metadata-sroa.ll
llvm/test/Transforms/SROA/non-capturing-call-readonly.ll
llvm/test/Transforms/SROA/non-integral-pointers.ll
llvm/test/Transforms/SROA/phi-and-select.ll
llvm/test/Transforms/SROA/phi-catchswitch.ll
llvm/test/Transforms/SROA/ppcf128-no-fold.ll
llvm/test/Transforms/SROA/pr26972.ll
llvm/test/Transforms/SROA/pr37267.ll
llvm/test/Transforms/SROA/preserve-nonnull.ll
llvm/test/Transforms/SROA/select-gep.ll
llvm/test/Transforms/SROA/select-load.ll
llvm/test/Transforms/SROA/slice-order-independence.ll
llvm/test/Transforms/SROA/tbaa-struct2.ll
llvm/test/Transforms/SROA/vector-lifetime-intrinsic.ll
llvm/test/Transforms/SROA/vector-promotion-different-size.ll
llvm/test/Transforms/SROA/vector-promotion.ll
llvm/test/Transforms/SROA/vectors-of-pointers.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/SROA/alignment.ll b/llvm/test/Transforms/SROA/alignment.ll
index 66da09cd52d2..223075830cb7 100644
--- a/llvm/test/Transforms/SROA/alignment.ll
+++ b/llvm/test/Transforms/SROA/alignment.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=sroa -S | FileCheck %s
-; RUN: opt -passes='debugify,function(sroa)' -S < %s | FileCheck %s -check-prefix DEBUGLOC
+; RUN: opt -passes='debugify,function(sroa)' -S < %s | FileCheck %s -check-prefix CHECK-DEBUGLOC
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
@@ -19,23 +19,22 @@ define void @test1(ptr %a, ptr %b) {
; CHECK-NEXT: store i8 [[ALLOCA_SROA_3_0_COPYLOAD]], ptr [[ALLOCA_SROA_3_0_GEP_B_SROA_IDX]], align 1
; CHECK-NEXT: ret void
;
-; DEBUGLOC-LABEL: @test1(
-; DEBUGLOC-NEXT: entry:
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META9:![0-9]+]], metadata !DIExpression()), !dbg [[DBG14:![0-9]+]]
-; DEBUGLOC-NEXT: [[GEP_A:%.*]] = getelementptr { i8, i8 }, ptr [[A:%.*]], i32 0, i32 0, !dbg [[DBG15:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr [[GEP_A]], metadata [[META11:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META12:![0-9]+]], metadata !DIExpression()), !dbg [[DBG16:![0-9]+]]
-; DEBUGLOC-NEXT: [[GEP_B:%.*]] = getelementptr { i8, i8 }, ptr [[B:%.*]], i32 0, i32 0, !dbg [[DBG17:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr [[GEP_B]], metadata [[META13:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17]]
-; DEBUGLOC-NEXT: [[ALLOCA_SROA_0_0_COPYLOAD:%.*]] = load i8, ptr [[GEP_A]], align 16, !dbg [[DBG18:![0-9]+]]
-; DEBUGLOC-NEXT: [[ALLOCA_SROA_3_0_GEP_A_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[GEP_A]], i64 1, !dbg [[DBG18]]
-; DEBUGLOC-NEXT: [[ALLOCA_SROA_3_0_COPYLOAD:%.*]] = load i8, ptr [[ALLOCA_SROA_3_0_GEP_A_SROA_IDX]], align 1, !dbg [[DBG18]]
-; DEBUGLOC-NEXT: store i8 [[ALLOCA_SROA_0_0_COPYLOAD]], ptr [[GEP_B]], align 16, !dbg [[DBG19:![0-9]+]]
-; DEBUGLOC-NEXT: [[ALLOCA_SROA_3_0_GEP_B_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[GEP_B]], i64 1, !dbg [[DBG19]]
-; DEBUGLOC-NEXT: store i8 [[ALLOCA_SROA_3_0_COPYLOAD]], ptr [[ALLOCA_SROA_3_0_GEP_B_SROA_IDX]], align 1, !dbg [[DBG19]]
-; DEBUGLOC-NEXT: ret void, !dbg [[DBG20:![0-9]+]]
+; CHECK-DEBUGLOC-LABEL: @test1(
+; CHECK-DEBUGLOC-NEXT: entry:
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META9:![0-9]+]], metadata !DIExpression()), !dbg [[DBG14:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[GEP_A:%.*]] = getelementptr { i8, i8 }, ptr [[A:%.*]], i32 0, i32 0, !dbg [[DBG15:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr [[GEP_A]], metadata [[META11:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META12:![0-9]+]], metadata !DIExpression()), !dbg [[DBG16:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[GEP_B:%.*]] = getelementptr { i8, i8 }, ptr [[B:%.*]], i32 0, i32 0, !dbg [[DBG17:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr [[GEP_B]], metadata [[META13:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17]]
+; CHECK-DEBUGLOC-NEXT: [[ALLOCA_SROA_0_0_COPYLOAD:%.*]] = load i8, ptr [[GEP_A]], align 16, !dbg [[DBG18:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[ALLOCA_SROA_3_0_GEP_A_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[GEP_A]], i64 1, !dbg [[DBG18]]
+; CHECK-DEBUGLOC-NEXT: [[ALLOCA_SROA_3_0_COPYLOAD:%.*]] = load i8, ptr [[ALLOCA_SROA_3_0_GEP_A_SROA_IDX]], align 1, !dbg [[DBG18]]
+; CHECK-DEBUGLOC-NEXT: store i8 [[ALLOCA_SROA_0_0_COPYLOAD]], ptr [[GEP_B]], align 16, !dbg [[DBG19:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[ALLOCA_SROA_3_0_GEP_B_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[GEP_B]], i64 1, !dbg [[DBG19]]
+; CHECK-DEBUGLOC-NEXT: store i8 [[ALLOCA_SROA_3_0_COPYLOAD]], ptr [[ALLOCA_SROA_3_0_GEP_B_SROA_IDX]], align 1, !dbg [[DBG19]]
+; CHECK-DEBUGLOC-NEXT: ret void, !dbg [[DBG20:![0-9]+]]
;
-
entry:
%alloca = alloca { i8, i8 }, align 16
%gep_a = getelementptr { i8, i8 }, ptr %a, i32 0, i32 0
@@ -50,6 +49,8 @@ entry:
}
define void @test2() {
+; Check that when sroa rewrites the alloca partition
+; it preserves the original debuglocation.
; CHECK-LABEL: @test2(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca i16, align 2
@@ -60,24 +61,20 @@ define void @test2() {
; CHECK-NEXT: store i8 42, ptr [[A_SROA_0_1_GEP2_SROA_IDX2]], align 1
; CHECK-NEXT: ret void
;
-; DEBUGLOC-LABEL: @test2(
-; DEBUGLOC-NEXT: entry:
-; DEBUGLOC-NEXT: [[A_SROA_0:%.*]] = alloca i16, align 2, !dbg [[DBG28:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META23:![0-9]+]], metadata !DIExpression()), !dbg [[DBG28]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META24:![0-9]+]], metadata !DIExpression()), !dbg [[DBG29:![0-9]+]]
-; DEBUGLOC-NEXT: store volatile i16 0, ptr [[A_SROA_0]], align 2, !dbg [[DBG30:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META25:![0-9]+]], metadata !DIExpression()), !dbg [[DBG31:![0-9]+]]
-; DEBUGLOC-NEXT: [[A_SROA_0_1_GEP2_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[A_SROA_0]], i64 1, !dbg [[DBG32:![0-9]+]]
-; DEBUGLOC-NEXT: [[A_SROA_0_1_A_SROA_0_2_RESULT:%.*]] = load i8, ptr [[A_SROA_0_1_GEP2_SROA_IDX]], align 1, !dbg [[DBG32]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata i8 [[A_SROA_0_1_A_SROA_0_2_RESULT]], metadata [[META26:![0-9]+]], metadata !DIExpression()), !dbg [[DBG32]]
-; DEBUGLOC-NEXT: [[A_SROA_0_1_GEP2_SROA_IDX2:%.*]] = getelementptr inbounds i8, ptr [[A_SROA_0]], i64 1, !dbg [[DBG33:![0-9]+]]
-; DEBUGLOC-NEXT: store i8 42, ptr [[A_SROA_0_1_GEP2_SROA_IDX2]], align 1, !dbg [[DBG33]]
-; DEBUGLOC-NEXT: ret void, !dbg [[DBG34:![0-9]+]]
+; CHECK-DEBUGLOC-LABEL: @test2(
+; CHECK-DEBUGLOC-NEXT: entry:
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_0:%.*]] = alloca i16, align 2, !dbg [[DBG28:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META23:![0-9]+]], metadata !DIExpression()), !dbg [[DBG28]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META24:![0-9]+]], metadata !DIExpression()), !dbg [[DBG29:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: store volatile i16 0, ptr [[A_SROA_0]], align 2, !dbg [[DBG30:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META25:![0-9]+]], metadata !DIExpression()), !dbg [[DBG31:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_0_1_GEP2_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[A_SROA_0]], i64 1, !dbg [[DBG32:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_0_1_A_SROA_0_2_RESULT:%.*]] = load i8, ptr [[A_SROA_0_1_GEP2_SROA_IDX]], align 1, !dbg [[DBG32]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata i8 [[A_SROA_0_1_A_SROA_0_2_RESULT]], metadata [[META26:![0-9]+]], metadata !DIExpression()), !dbg [[DBG32]]
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_0_1_GEP2_SROA_IDX2:%.*]] = getelementptr inbounds i8, ptr [[A_SROA_0]], i64 1, !dbg [[DBG33:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: store i8 42, ptr [[A_SROA_0_1_GEP2_SROA_IDX2]], align 1, !dbg [[DBG33]]
+; CHECK-DEBUGLOC-NEXT: ret void, !dbg [[DBG34:![0-9]+]]
;
-
-; Check that when sroa rewrites the alloca partition
-; it preserves the original DebugLocation.
-
entry:
%a = alloca { i8, i8, i8, i8 }, align 2 ; "line 9" to -debugify
%gep1 = getelementptr { i8, i8, i8, i8 }, ptr %a, i32 0, i32 1
@@ -90,20 +87,21 @@ entry:
define void @PR13920(ptr %a, ptr %b) {
; Test that alignments on memcpy intrinsics get propagated to loads and stores.
+;
+;
; CHECK-LABEL: @PR13920(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[AA_0_COPYLOAD:%.*]] = load <2 x i64>, ptr [[A:%.*]], align 2
; CHECK-NEXT: store <2 x i64> [[AA_0_COPYLOAD]], ptr [[B:%.*]], align 2
; CHECK-NEXT: ret void
;
-; DEBUGLOC-LABEL: @PR13920(
-; DEBUGLOC-NEXT: entry:
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META37:![0-9]+]], metadata !DIExpression()), !dbg [[DBG38:![0-9]+]]
-; DEBUGLOC-NEXT: [[AA_0_COPYLOAD:%.*]] = load <2 x i64>, ptr [[A:%.*]], align 2, !dbg [[DBG39:![0-9]+]]
-; DEBUGLOC-NEXT: store <2 x i64> [[AA_0_COPYLOAD]], ptr [[B:%.*]], align 2, !dbg [[DBG40:![0-9]+]]
-; DEBUGLOC-NEXT: ret void, !dbg [[DBG41:![0-9]+]]
+; CHECK-DEBUGLOC-LABEL: @PR13920(
+; CHECK-DEBUGLOC-NEXT: entry:
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META37:![0-9]+]], metadata !DIExpression()), !dbg [[DBG38:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[AA_0_COPYLOAD:%.*]] = load <2 x i64>, ptr [[A:%.*]], align 2, !dbg [[DBG39:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: store <2 x i64> [[AA_0_COPYLOAD]], ptr [[B:%.*]], align 2, !dbg [[DBG40:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: ret void, !dbg [[DBG41:![0-9]+]]
;
-
entry:
%aa = alloca <2 x i64>, align 16
call void @llvm.memcpy.p0.p0.i32(ptr align 2 %aa, ptr align 2 %a, i32 16, i1 false)
@@ -116,6 +114,8 @@ define void @test3(ptr %x) {
; provide the needed explicit alignment that code using the alloca may be
; expecting. However, also check that any offset within an alloca can in turn
; reduce the alignment.
+;
+;
; CHECK-LABEL: @test3(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca [22 x i8], align 8
@@ -124,18 +124,17 @@ define void @test3(ptr %x) {
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[B_SROA_0]], ptr align 2 [[X]], i32 18, i1 false)
; CHECK-NEXT: ret void
;
-; DEBUGLOC-LABEL: @test3(
-; DEBUGLOC-NEXT: entry:
-; DEBUGLOC-NEXT: [[A_SROA_0:%.*]] = alloca [22 x i8], align 8, !dbg [[DBG47:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META44:![0-9]+]], metadata !DIExpression()), !dbg [[DBG47]]
-; DEBUGLOC-NEXT: [[B_SROA_0:%.*]] = alloca [18 x i8], align 2, !dbg [[DBG48:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META45:![0-9]+]], metadata !DIExpression()), !dbg [[DBG48]]
-; DEBUGLOC-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[A_SROA_0]], ptr align 8 [[X:%.*]], i32 22, i1 false), !dbg [[DBG49:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META46:![0-9]+]], metadata !DIExpression()), !dbg [[DBG50:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[B_SROA_0]], ptr align 2 [[X]], i32 18, i1 false), !dbg [[DBG51:![0-9]+]]
-; DEBUGLOC-NEXT: ret void, !dbg [[DBG52:![0-9]+]]
+; CHECK-DEBUGLOC-LABEL: @test3(
+; CHECK-DEBUGLOC-NEXT: entry:
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_0:%.*]] = alloca [22 x i8], align 8, !dbg [[DBG47:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META44:![0-9]+]], metadata !DIExpression()), !dbg [[DBG47]]
+; CHECK-DEBUGLOC-NEXT: [[B_SROA_0:%.*]] = alloca [18 x i8], align 2, !dbg [[DBG48:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META45:![0-9]+]], metadata !DIExpression()), !dbg [[DBG48]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[A_SROA_0]], ptr align 8 [[X:%.*]], i32 22, i1 false), !dbg [[DBG49:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META46:![0-9]+]], metadata !DIExpression()), !dbg [[DBG50:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[B_SROA_0]], ptr align 2 [[X]], i32 18, i1 false), !dbg [[DBG51:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: ret void, !dbg [[DBG52:![0-9]+]]
;
-
entry:
%a = alloca { ptr, ptr, ptr }
%b = alloca { ptr, ptr, ptr }
@@ -150,6 +149,8 @@ define void @test5() {
; of volatile in this test case is just to force the loads and stores to not be
; split or promoted out of existence.
;
+;
+;
; CHECK-LABEL: @test5(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca [9 x i8], align 1
@@ -163,27 +164,26 @@ define void @test5() {
; CHECK-NEXT: [[A_SROA_3_7_A_SROA_3_16_WEIRD_LOAD2:%.*]] = load volatile i16, ptr [[A_SROA_3_7_WEIRD_GEP2_SROA_IDX]], align 1
; CHECK-NEXT: ret void
;
-; DEBUGLOC-LABEL: @test5(
-; DEBUGLOC-NEXT: entry:
-; DEBUGLOC-NEXT: [[A_SROA_0:%.*]] = alloca [9 x i8], align 1, !dbg [[DBG63:![0-9]+]]
-; DEBUGLOC-NEXT: [[A_SROA_3:%.*]] = alloca [9 x i8], align 1, !dbg [[DBG63]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META55:![0-9]+]], metadata !DIExpression()), !dbg [[DBG63]]
-; DEBUGLOC-NEXT: store volatile double 0.000000e+00, ptr [[A_SROA_0]], align 1, !dbg [[DBG64:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META56:![0-9]+]], metadata !DIExpression()), !dbg [[DBG65:![0-9]+]]
-; DEBUGLOC-NEXT: [[A_SROA_0_7_WEIRD_GEP1_SROA_IDX1:%.*]] = getelementptr inbounds i8, ptr [[A_SROA_0]], i64 7, !dbg [[DBG66:![0-9]+]]
-; DEBUGLOC-NEXT: [[A_SROA_0_7_A_SROA_0_7_WEIRD_LOAD1:%.*]] = load volatile i16, ptr [[A_SROA_0_7_WEIRD_GEP1_SROA_IDX1]], align 1, !dbg [[DBG66]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata i16 [[A_SROA_0_7_A_SROA_0_7_WEIRD_LOAD1]], metadata [[META57:![0-9]+]], metadata !DIExpression()), !dbg [[DBG66]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META59:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67:![0-9]+]]
-; DEBUGLOC-NEXT: [[A_SROA_0_0_A_SROA_0_0_D1:%.*]] = load double, ptr [[A_SROA_0]], align 1, !dbg [[DBG68:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata double [[A_SROA_0_0_A_SROA_0_0_D1]], metadata [[META60:![0-9]+]], metadata !DIExpression()), !dbg [[DBG68]]
-; DEBUGLOC-NEXT: store volatile double [[A_SROA_0_0_A_SROA_0_0_D1]], ptr [[A_SROA_3]], align 1, !dbg [[DBG69:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META61:![0-9]+]], metadata !DIExpression()), !dbg [[DBG70:![0-9]+]]
-; DEBUGLOC-NEXT: [[A_SROA_3_7_WEIRD_GEP2_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[A_SROA_3]], i64 7, !dbg [[DBG71:![0-9]+]]
-; DEBUGLOC-NEXT: [[A_SROA_3_7_A_SROA_3_16_WEIRD_LOAD2:%.*]] = load volatile i16, ptr [[A_SROA_3_7_WEIRD_GEP2_SROA_IDX]], align 1, !dbg [[DBG71]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata i16 [[A_SROA_3_7_A_SROA_3_16_WEIRD_LOAD2]], metadata [[META62:![0-9]+]], metadata !DIExpression()), !dbg [[DBG71]]
-; DEBUGLOC-NEXT: ret void, !dbg [[DBG72:![0-9]+]]
+; CHECK-DEBUGLOC-LABEL: @test5(
+; CHECK-DEBUGLOC-NEXT: entry:
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_0:%.*]] = alloca [9 x i8], align 1, !dbg [[DBG63:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_3:%.*]] = alloca [9 x i8], align 1, !dbg [[DBG63]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META55:![0-9]+]], metadata !DIExpression()), !dbg [[DBG63]]
+; CHECK-DEBUGLOC-NEXT: store volatile double 0.000000e+00, ptr [[A_SROA_0]], align 1, !dbg [[DBG64:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META56:![0-9]+]], metadata !DIExpression()), !dbg [[DBG65:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_0_7_WEIRD_GEP1_SROA_IDX1:%.*]] = getelementptr inbounds i8, ptr [[A_SROA_0]], i64 7, !dbg [[DBG66:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_0_7_A_SROA_0_7_WEIRD_LOAD1:%.*]] = load volatile i16, ptr [[A_SROA_0_7_WEIRD_GEP1_SROA_IDX1]], align 1, !dbg [[DBG66]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata i16 [[A_SROA_0_7_A_SROA_0_7_WEIRD_LOAD1]], metadata [[META57:![0-9]+]], metadata !DIExpression()), !dbg [[DBG66]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META59:![0-9]+]], metadata !DIExpression()), !dbg [[DBG67:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_0_0_A_SROA_0_0_D1:%.*]] = load double, ptr [[A_SROA_0]], align 1, !dbg [[DBG68:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata double [[A_SROA_0_0_A_SROA_0_0_D1]], metadata [[META60:![0-9]+]], metadata !DIExpression()), !dbg [[DBG68]]
+; CHECK-DEBUGLOC-NEXT: store volatile double [[A_SROA_0_0_A_SROA_0_0_D1]], ptr [[A_SROA_3]], align 1, !dbg [[DBG69:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META61:![0-9]+]], metadata !DIExpression()), !dbg [[DBG70:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_3_7_WEIRD_GEP2_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[A_SROA_3]], i64 7, !dbg [[DBG71:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_3_7_A_SROA_3_16_WEIRD_LOAD2:%.*]] = load volatile i16, ptr [[A_SROA_3_7_WEIRD_GEP2_SROA_IDX]], align 1, !dbg [[DBG71]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata i16 [[A_SROA_3_7_A_SROA_3_16_WEIRD_LOAD2]], metadata [[META62:![0-9]+]], metadata !DIExpression()), !dbg [[DBG71]]
+; CHECK-DEBUGLOC-NEXT: ret void, !dbg [[DBG72:![0-9]+]]
;
-
entry:
%a = alloca [18 x i8]
store volatile double 0.0, ptr %a, align 1
@@ -202,6 +202,8 @@ entry:
define void @test6() {
; We should set the alignment on all load and store operations; make sure
; we choose an appropriate alignment.
+;
+;
; CHECK-LABEL: @test6(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca double, align 8
@@ -211,19 +213,18 @@ define void @test6() {
; CHECK-NEXT: store volatile double [[A_SROA_0_0_A_SROA_0_0_VAL]], ptr [[A_SROA_2]], align 8
; CHECK-NEXT: ret void
;
-; DEBUGLOC-LABEL: @test6(
-; DEBUGLOC-NEXT: entry:
-; DEBUGLOC-NEXT: [[A_SROA_0:%.*]] = alloca double, align 8, !dbg [[DBG78:![0-9]+]]
-; DEBUGLOC-NEXT: [[A_SROA_2:%.*]] = alloca double, align 8, !dbg [[DBG78]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META75:![0-9]+]], metadata !DIExpression()), !dbg [[DBG78]]
-; DEBUGLOC-NEXT: store volatile double 0.000000e+00, ptr [[A_SROA_0]], align 8, !dbg [[DBG79:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META76:![0-9]+]], metadata !DIExpression()), !dbg [[DBG80:![0-9]+]]
-; DEBUGLOC-NEXT: [[A_SROA_0_0_A_SROA_0_0_VAL:%.*]] = load double, ptr [[A_SROA_0]], align 8, !dbg [[DBG81:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata double [[A_SROA_0_0_A_SROA_0_0_VAL]], metadata [[META77:![0-9]+]], metadata !DIExpression()), !dbg [[DBG81]]
-; DEBUGLOC-NEXT: store volatile double [[A_SROA_0_0_A_SROA_0_0_VAL]], ptr [[A_SROA_2]], align 8, !dbg [[DBG82:![0-9]+]]
-; DEBUGLOC-NEXT: ret void, !dbg [[DBG83:![0-9]+]]
+; CHECK-DEBUGLOC-LABEL: @test6(
+; CHECK-DEBUGLOC-NEXT: entry:
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_0:%.*]] = alloca double, align 8, !dbg [[DBG78:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_2:%.*]] = alloca double, align 8, !dbg [[DBG78]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META75:![0-9]+]], metadata !DIExpression()), !dbg [[DBG78]]
+; CHECK-DEBUGLOC-NEXT: store volatile double 0.000000e+00, ptr [[A_SROA_0]], align 8, !dbg [[DBG79:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META76:![0-9]+]], metadata !DIExpression()), !dbg [[DBG80:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_0_0_A_SROA_0_0_VAL:%.*]] = load double, ptr [[A_SROA_0]], align 8, !dbg [[DBG81:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata double [[A_SROA_0_0_A_SROA_0_0_VAL]], metadata [[META77:![0-9]+]], metadata !DIExpression()), !dbg [[DBG81]]
+; CHECK-DEBUGLOC-NEXT: store volatile double [[A_SROA_0_0_A_SROA_0_0_VAL]], ptr [[A_SROA_2]], align 8, !dbg [[DBG82:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: ret void, !dbg [[DBG83:![0-9]+]]
;
-
entry:
%a = alloca [16 x i8]
store volatile double 0.0, ptr %a, align 1
@@ -238,6 +239,8 @@ entry:
define void @test7(ptr %out) {
; Test that we properly compute the destination alignment when rewriting
; memcpys as direct loads or stores.
+;
+;
; CHECK-LABEL: @test7(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0_0_COPYLOAD:%.*]] = load double, ptr [[OUT:%.*]], align 1
@@ -248,21 +251,20 @@ define void @test7(ptr %out) {
; CHECK-NEXT: store double [[A_SROA_0_0_COPYLOAD]], ptr [[A_SROA_4_0_OUT_SROA_IDX2]], align 1
; CHECK-NEXT: ret void
;
-; DEBUGLOC-LABEL: @test7(
-; DEBUGLOC-NEXT: entry:
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META86:![0-9]+]], metadata !DIExpression()), !dbg [[DBG90:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META87:![0-9]+]], metadata !DIExpression()), !dbg [[DBG91:![0-9]+]]
-; DEBUGLOC-NEXT: [[A_SROA_0_0_COPYLOAD:%.*]] = load double, ptr [[OUT:%.*]], align 1, !dbg [[DBG92:![0-9]+]]
-; DEBUGLOC-NEXT: [[A_SROA_4_0_OUT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[OUT]], i64 8, !dbg [[DBG92]]
-; DEBUGLOC-NEXT: [[A_SROA_4_0_COPYLOAD:%.*]] = load double, ptr [[A_SROA_4_0_OUT_SROA_IDX]], align 1, !dbg [[DBG92]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata double [[A_SROA_4_0_COPYLOAD]], metadata [[META88:![0-9]+]], metadata !DIExpression()), !dbg [[DBG93:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata double [[A_SROA_0_0_COPYLOAD]], metadata [[META89:![0-9]+]], metadata !DIExpression()), !dbg [[DBG94:![0-9]+]]
-; DEBUGLOC-NEXT: store double [[A_SROA_4_0_COPYLOAD]], ptr [[OUT]], align 1, !dbg [[DBG95:![0-9]+]]
-; DEBUGLOC-NEXT: [[A_SROA_4_0_OUT_SROA_IDX2:%.*]] = getelementptr inbounds i8, ptr [[OUT]], i64 8, !dbg [[DBG95]]
-; DEBUGLOC-NEXT: store double [[A_SROA_0_0_COPYLOAD]], ptr [[A_SROA_4_0_OUT_SROA_IDX2]], align 1, !dbg [[DBG95]]
-; DEBUGLOC-NEXT: ret void, !dbg [[DBG96:![0-9]+]]
+; CHECK-DEBUGLOC-LABEL: @test7(
+; CHECK-DEBUGLOC-NEXT: entry:
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META86:![0-9]+]], metadata !DIExpression()), !dbg [[DBG90:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META87:![0-9]+]], metadata !DIExpression()), !dbg [[DBG91:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_0_0_COPYLOAD:%.*]] = load double, ptr [[OUT:%.*]], align 1, !dbg [[DBG92:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_4_0_OUT_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[OUT]], i64 8, !dbg [[DBG92]]
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_4_0_COPYLOAD:%.*]] = load double, ptr [[A_SROA_4_0_OUT_SROA_IDX]], align 1, !dbg [[DBG92]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata double [[A_SROA_4_0_COPYLOAD]], metadata [[META88:![0-9]+]], metadata !DIExpression()), !dbg [[DBG93:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata double [[A_SROA_0_0_COPYLOAD]], metadata [[META89:![0-9]+]], metadata !DIExpression()), !dbg [[DBG94:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: store double [[A_SROA_4_0_COPYLOAD]], ptr [[OUT]], align 1, !dbg [[DBG95:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[A_SROA_4_0_OUT_SROA_IDX2:%.*]] = getelementptr inbounds i8, ptr [[OUT]], i64 8, !dbg [[DBG95]]
+; CHECK-DEBUGLOC-NEXT: store double [[A_SROA_0_0_COPYLOAD]], ptr [[A_SROA_4_0_OUT_SROA_IDX2]], align 1, !dbg [[DBG95]]
+; CHECK-DEBUGLOC-NEXT: ret void, !dbg [[DBG96:![0-9]+]]
;
-
entry:
%a = alloca [16 x i8]
%raw2 = getelementptr inbounds [16 x i8], ptr %a, i32 0, i32 8
@@ -301,29 +303,28 @@ define void @test8() {
; CHECK-NEXT: [[VAL_FCA_4_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_3_INSERT]], i32 [[VAL_FCA_4_LOAD]], 4
; CHECK-NEXT: ret void
;
-; DEBUGLOC-LABEL: @test8(
-; DEBUGLOC-NEXT: [[PTR:%.*]] = alloca [5 x i32], align 1, !dbg [[DBG102:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr [[PTR]], metadata [[META99:![0-9]+]], metadata !DIExpression()), !dbg [[DBG102]]
-; DEBUGLOC-NEXT: call void @populate(ptr [[PTR]]), !dbg [[DBG103:![0-9]+]]
-; DEBUGLOC-NEXT: [[VAL_FCA_0_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 0, !dbg [[DBG104:![0-9]+]]
-; DEBUGLOC-NEXT: [[VAL_FCA_0_LOAD:%.*]] = load i32, ptr [[VAL_FCA_0_GEP]], align 1, !dbg [[DBG104]]
-; DEBUGLOC-NEXT: [[VAL_FCA_0_INSERT:%.*]] = insertvalue [5 x i32] poison, i32 [[VAL_FCA_0_LOAD]], 0, !dbg [[DBG104]]
-; DEBUGLOC-NEXT: [[VAL_FCA_1_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 1, !dbg [[DBG104]]
-; DEBUGLOC-NEXT: [[VAL_FCA_1_LOAD:%.*]] = load i32, ptr [[VAL_FCA_1_GEP]], align 1, !dbg [[DBG104]]
-; DEBUGLOC-NEXT: [[VAL_FCA_1_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_0_INSERT]], i32 [[VAL_FCA_1_LOAD]], 1, !dbg [[DBG104]]
-; DEBUGLOC-NEXT: [[VAL_FCA_2_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 2, !dbg [[DBG104]]
-; DEBUGLOC-NEXT: [[VAL_FCA_2_LOAD:%.*]] = load i32, ptr [[VAL_FCA_2_GEP]], align 1, !dbg [[DBG104]]
-; DEBUGLOC-NEXT: [[VAL_FCA_2_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_1_INSERT]], i32 [[VAL_FCA_2_LOAD]], 2, !dbg [[DBG104]]
-; DEBUGLOC-NEXT: [[VAL_FCA_3_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 3, !dbg [[DBG104]]
-; DEBUGLOC-NEXT: [[VAL_FCA_3_LOAD:%.*]] = load i32, ptr [[VAL_FCA_3_GEP]], align 1, !dbg [[DBG104]]
-; DEBUGLOC-NEXT: [[VAL_FCA_3_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_2_INSERT]], i32 [[VAL_FCA_3_LOAD]], 3, !dbg [[DBG104]]
-; DEBUGLOC-NEXT: [[VAL_FCA_4_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 4, !dbg [[DBG104]]
-; DEBUGLOC-NEXT: [[VAL_FCA_4_LOAD:%.*]] = load i32, ptr [[VAL_FCA_4_GEP]], align 1, !dbg [[DBG104]]
-; DEBUGLOC-NEXT: [[VAL_FCA_4_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_3_INSERT]], i32 [[VAL_FCA_4_LOAD]], 4, !dbg [[DBG104]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata [5 x i32] [[VAL_FCA_4_INSERT]], metadata [[META100:![0-9]+]], metadata !DIExpression()), !dbg [[DBG104]]
-; DEBUGLOC-NEXT: ret void, !dbg [[DBG105:![0-9]+]]
+; CHECK-DEBUGLOC-LABEL: @test8(
+; CHECK-DEBUGLOC-NEXT: [[PTR:%.*]] = alloca [5 x i32], align 1, !dbg [[DBG102:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr [[PTR]], metadata [[META99:![0-9]+]], metadata !DIExpression()), !dbg [[DBG102]]
+; CHECK-DEBUGLOC-NEXT: call void @populate(ptr [[PTR]]), !dbg [[DBG103:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_0_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 0, !dbg [[DBG104:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_0_LOAD:%.*]] = load i32, ptr [[VAL_FCA_0_GEP]], align 1, !dbg [[DBG104]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_0_INSERT:%.*]] = insertvalue [5 x i32] poison, i32 [[VAL_FCA_0_LOAD]], 0, !dbg [[DBG104]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_1_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 1, !dbg [[DBG104]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_1_LOAD:%.*]] = load i32, ptr [[VAL_FCA_1_GEP]], align 1, !dbg [[DBG104]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_1_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_0_INSERT]], i32 [[VAL_FCA_1_LOAD]], 1, !dbg [[DBG104]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_2_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 2, !dbg [[DBG104]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_2_LOAD:%.*]] = load i32, ptr [[VAL_FCA_2_GEP]], align 1, !dbg [[DBG104]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_2_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_1_INSERT]], i32 [[VAL_FCA_2_LOAD]], 2, !dbg [[DBG104]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_3_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 3, !dbg [[DBG104]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_3_LOAD:%.*]] = load i32, ptr [[VAL_FCA_3_GEP]], align 1, !dbg [[DBG104]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_3_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_2_INSERT]], i32 [[VAL_FCA_3_LOAD]], 3, !dbg [[DBG104]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_4_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 4, !dbg [[DBG104]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_4_LOAD:%.*]] = load i32, ptr [[VAL_FCA_4_GEP]], align 1, !dbg [[DBG104]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_4_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_3_INSERT]], i32 [[VAL_FCA_4_LOAD]], 4, !dbg [[DBG104]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata [5 x i32] [[VAL_FCA_4_INSERT]], metadata [[META100:![0-9]+]], metadata !DIExpression()), !dbg [[DBG104]]
+; CHECK-DEBUGLOC-NEXT: ret void, !dbg [[DBG105:![0-9]+]]
;
-
%ptr = alloca [5 x i32], align 1
call void @populate(ptr %ptr)
%val = load [5 x i32], ptr %ptr, align 1
@@ -351,29 +352,28 @@ define void @test9() {
; CHECK-NEXT: [[VAL_FCA_4_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_3_INSERT]], i32 [[VAL_FCA_4_LOAD]], 4
; CHECK-NEXT: ret void
;
-; DEBUGLOC-LABEL: @test9(
-; DEBUGLOC-NEXT: [[PTR:%.*]] = alloca [5 x i32], align 8, !dbg [[DBG110:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr [[PTR]], metadata [[META108:![0-9]+]], metadata !DIExpression()), !dbg [[DBG110]]
-; DEBUGLOC-NEXT: call void @populate(ptr [[PTR]]), !dbg [[DBG111:![0-9]+]]
-; DEBUGLOC-NEXT: [[VAL_FCA_0_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 0, !dbg [[DBG112:![0-9]+]]
-; DEBUGLOC-NEXT: [[VAL_FCA_0_LOAD:%.*]] = load i32, ptr [[VAL_FCA_0_GEP]], align 8, !dbg [[DBG112]]
-; DEBUGLOC-NEXT: [[VAL_FCA_0_INSERT:%.*]] = insertvalue [5 x i32] poison, i32 [[VAL_FCA_0_LOAD]], 0, !dbg [[DBG112]]
-; DEBUGLOC-NEXT: [[VAL_FCA_1_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 1, !dbg [[DBG112]]
-; DEBUGLOC-NEXT: [[VAL_FCA_1_LOAD:%.*]] = load i32, ptr [[VAL_FCA_1_GEP]], align 4, !dbg [[DBG112]]
-; DEBUGLOC-NEXT: [[VAL_FCA_1_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_0_INSERT]], i32 [[VAL_FCA_1_LOAD]], 1, !dbg [[DBG112]]
-; DEBUGLOC-NEXT: [[VAL_FCA_2_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 2, !dbg [[DBG112]]
-; DEBUGLOC-NEXT: [[VAL_FCA_2_LOAD:%.*]] = load i32, ptr [[VAL_FCA_2_GEP]], align 8, !dbg [[DBG112]]
-; DEBUGLOC-NEXT: [[VAL_FCA_2_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_1_INSERT]], i32 [[VAL_FCA_2_LOAD]], 2, !dbg [[DBG112]]
-; DEBUGLOC-NEXT: [[VAL_FCA_3_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 3, !dbg [[DBG112]]
-; DEBUGLOC-NEXT: [[VAL_FCA_3_LOAD:%.*]] = load i32, ptr [[VAL_FCA_3_GEP]], align 4, !dbg [[DBG112]]
-; DEBUGLOC-NEXT: [[VAL_FCA_3_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_2_INSERT]], i32 [[VAL_FCA_3_LOAD]], 3, !dbg [[DBG112]]
-; DEBUGLOC-NEXT: [[VAL_FCA_4_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 4, !dbg [[DBG112]]
-; DEBUGLOC-NEXT: [[VAL_FCA_4_LOAD:%.*]] = load i32, ptr [[VAL_FCA_4_GEP]], align 8, !dbg [[DBG112]]
-; DEBUGLOC-NEXT: [[VAL_FCA_4_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_3_INSERT]], i32 [[VAL_FCA_4_LOAD]], 4, !dbg [[DBG112]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata [5 x i32] [[VAL_FCA_4_INSERT]], metadata [[META109:![0-9]+]], metadata !DIExpression()), !dbg [[DBG112]]
-; DEBUGLOC-NEXT: ret void, !dbg [[DBG113:![0-9]+]]
+; CHECK-DEBUGLOC-LABEL: @test9(
+; CHECK-DEBUGLOC-NEXT: [[PTR:%.*]] = alloca [5 x i32], align 8, !dbg [[DBG110:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr [[PTR]], metadata [[META108:![0-9]+]], metadata !DIExpression()), !dbg [[DBG110]]
+; CHECK-DEBUGLOC-NEXT: call void @populate(ptr [[PTR]]), !dbg [[DBG111:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_0_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 0, !dbg [[DBG112:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_0_LOAD:%.*]] = load i32, ptr [[VAL_FCA_0_GEP]], align 8, !dbg [[DBG112]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_0_INSERT:%.*]] = insertvalue [5 x i32] poison, i32 [[VAL_FCA_0_LOAD]], 0, !dbg [[DBG112]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_1_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 1, !dbg [[DBG112]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_1_LOAD:%.*]] = load i32, ptr [[VAL_FCA_1_GEP]], align 4, !dbg [[DBG112]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_1_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_0_INSERT]], i32 [[VAL_FCA_1_LOAD]], 1, !dbg [[DBG112]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_2_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 2, !dbg [[DBG112]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_2_LOAD:%.*]] = load i32, ptr [[VAL_FCA_2_GEP]], align 8, !dbg [[DBG112]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_2_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_1_INSERT]], i32 [[VAL_FCA_2_LOAD]], 2, !dbg [[DBG112]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_3_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 3, !dbg [[DBG112]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_3_LOAD:%.*]] = load i32, ptr [[VAL_FCA_3_GEP]], align 4, !dbg [[DBG112]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_3_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_2_INSERT]], i32 [[VAL_FCA_3_LOAD]], 3, !dbg [[DBG112]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_4_GEP:%.*]] = getelementptr inbounds [5 x i32], ptr [[PTR]], i32 0, i32 4, !dbg [[DBG112]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_4_LOAD:%.*]] = load i32, ptr [[VAL_FCA_4_GEP]], align 8, !dbg [[DBG112]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_4_INSERT:%.*]] = insertvalue [5 x i32] [[VAL_FCA_3_INSERT]], i32 [[VAL_FCA_4_LOAD]], 4, !dbg [[DBG112]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata [5 x i32] [[VAL_FCA_4_INSERT]], metadata [[META109:![0-9]+]], metadata !DIExpression()), !dbg [[DBG112]]
+; CHECK-DEBUGLOC-NEXT: ret void, !dbg [[DBG113:![0-9]+]]
;
-
%ptr = alloca [5 x i32], align 8
call void @populate(ptr %ptr)
%val = load [5 x i32], ptr %ptr, align 8
@@ -401,29 +401,28 @@ define void @test10() {
; CHECK-NEXT: [[VAL_FCA_3_1_INSERT:%.*]] = insertvalue { i32, i8, i8, { i8, i16 } } [[VAL_FCA_3_0_INSERT]], i16 [[VAL_FCA_3_1_LOAD]], 3, 1
; CHECK-NEXT: ret void
;
-; DEBUGLOC-LABEL: @test10(
-; DEBUGLOC-NEXT: [[PTR:%.*]] = alloca { i32, i8, i8, { i8, i16 } }, align 2, !dbg [[DBG119:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr [[PTR]], metadata [[META116:![0-9]+]], metadata !DIExpression()), !dbg [[DBG119]]
-; DEBUGLOC-NEXT: call void @populate(ptr [[PTR]]), !dbg [[DBG120:![0-9]+]]
-; DEBUGLOC-NEXT: [[VAL_FCA_0_GEP:%.*]] = getelementptr inbounds { i32, i8, i8, { i8, i16 } }, ptr [[PTR]], i32 0, i32 0, !dbg [[DBG121:![0-9]+]]
-; DEBUGLOC-NEXT: [[VAL_FCA_0_LOAD:%.*]] = load i32, ptr [[VAL_FCA_0_GEP]], align 2, !dbg [[DBG121]]
-; DEBUGLOC-NEXT: [[VAL_FCA_0_INSERT:%.*]] = insertvalue { i32, i8, i8, { i8, i16 } } poison, i32 [[VAL_FCA_0_LOAD]], 0, !dbg [[DBG121]]
-; DEBUGLOC-NEXT: [[VAL_FCA_1_GEP:%.*]] = getelementptr inbounds { i32, i8, i8, { i8, i16 } }, ptr [[PTR]], i32 0, i32 1, !dbg [[DBG121]]
-; DEBUGLOC-NEXT: [[VAL_FCA_1_LOAD:%.*]] = load i8, ptr [[VAL_FCA_1_GEP]], align 2, !dbg [[DBG121]]
-; DEBUGLOC-NEXT: [[VAL_FCA_1_INSERT:%.*]] = insertvalue { i32, i8, i8, { i8, i16 } } [[VAL_FCA_0_INSERT]], i8 [[VAL_FCA_1_LOAD]], 1, !dbg [[DBG121]]
-; DEBUGLOC-NEXT: [[VAL_FCA_2_GEP:%.*]] = getelementptr inbounds { i32, i8, i8, { i8, i16 } }, ptr [[PTR]], i32 0, i32 2, !dbg [[DBG121]]
-; DEBUGLOC-NEXT: [[VAL_FCA_2_LOAD:%.*]] = load i8, ptr [[VAL_FCA_2_GEP]], align 1, !dbg [[DBG121]]
-; DEBUGLOC-NEXT: [[VAL_FCA_2_INSERT:%.*]] = insertvalue { i32, i8, i8, { i8, i16 } } [[VAL_FCA_1_INSERT]], i8 [[VAL_FCA_2_LOAD]], 2, !dbg [[DBG121]]
-; DEBUGLOC-NEXT: [[VAL_FCA_3_0_GEP:%.*]] = getelementptr inbounds { i32, i8, i8, { i8, i16 } }, ptr [[PTR]], i32 0, i32 3, i32 0, !dbg [[DBG121]]
-; DEBUGLOC-NEXT: [[VAL_FCA_3_0_LOAD:%.*]] = load i8, ptr [[VAL_FCA_3_0_GEP]], align 2, !dbg [[DBG121]]
-; DEBUGLOC-NEXT: [[VAL_FCA_3_0_INSERT:%.*]] = insertvalue { i32, i8, i8, { i8, i16 } } [[VAL_FCA_2_INSERT]], i8 [[VAL_FCA_3_0_LOAD]], 3, 0, !dbg [[DBG121]]
-; DEBUGLOC-NEXT: [[VAL_FCA_3_1_GEP:%.*]] = getelementptr inbounds { i32, i8, i8, { i8, i16 } }, ptr [[PTR]], i32 0, i32 3, i32 1, !dbg [[DBG121]]
-; DEBUGLOC-NEXT: [[VAL_FCA_3_1_LOAD:%.*]] = load i16, ptr [[VAL_FCA_3_1_GEP]], align 2, !dbg [[DBG121]]
-; DEBUGLOC-NEXT: [[VAL_FCA_3_1_INSERT:%.*]] = insertvalue { i32, i8, i8, { i8, i16 } } [[VAL_FCA_3_0_INSERT]], i16 [[VAL_FCA_3_1_LOAD]], 3, 1, !dbg [[DBG121]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata { i32, i8, i8, { i8, i16 } } [[VAL_FCA_3_1_INSERT]], metadata [[META117:![0-9]+]], metadata !DIExpression()), !dbg [[DBG121]]
-; DEBUGLOC-NEXT: ret void, !dbg [[DBG122:![0-9]+]]
+; CHECK-DEBUGLOC-LABEL: @test10(
+; CHECK-DEBUGLOC-NEXT: [[PTR:%.*]] = alloca { i32, i8, i8, { i8, i16 } }, align 2, !dbg [[DBG119:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr [[PTR]], metadata [[META116:![0-9]+]], metadata !DIExpression()), !dbg [[DBG119]]
+; CHECK-DEBUGLOC-NEXT: call void @populate(ptr [[PTR]]), !dbg [[DBG120:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_0_GEP:%.*]] = getelementptr inbounds { i32, i8, i8, { i8, i16 } }, ptr [[PTR]], i32 0, i32 0, !dbg [[DBG121:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_0_LOAD:%.*]] = load i32, ptr [[VAL_FCA_0_GEP]], align 2, !dbg [[DBG121]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_0_INSERT:%.*]] = insertvalue { i32, i8, i8, { i8, i16 } } poison, i32 [[VAL_FCA_0_LOAD]], 0, !dbg [[DBG121]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_1_GEP:%.*]] = getelementptr inbounds { i32, i8, i8, { i8, i16 } }, ptr [[PTR]], i32 0, i32 1, !dbg [[DBG121]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_1_LOAD:%.*]] = load i8, ptr [[VAL_FCA_1_GEP]], align 2, !dbg [[DBG121]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_1_INSERT:%.*]] = insertvalue { i32, i8, i8, { i8, i16 } } [[VAL_FCA_0_INSERT]], i8 [[VAL_FCA_1_LOAD]], 1, !dbg [[DBG121]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_2_GEP:%.*]] = getelementptr inbounds { i32, i8, i8, { i8, i16 } }, ptr [[PTR]], i32 0, i32 2, !dbg [[DBG121]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_2_LOAD:%.*]] = load i8, ptr [[VAL_FCA_2_GEP]], align 1, !dbg [[DBG121]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_2_INSERT:%.*]] = insertvalue { i32, i8, i8, { i8, i16 } } [[VAL_FCA_1_INSERT]], i8 [[VAL_FCA_2_LOAD]], 2, !dbg [[DBG121]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_3_0_GEP:%.*]] = getelementptr inbounds { i32, i8, i8, { i8, i16 } }, ptr [[PTR]], i32 0, i32 3, i32 0, !dbg [[DBG121]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_3_0_LOAD:%.*]] = load i8, ptr [[VAL_FCA_3_0_GEP]], align 2, !dbg [[DBG121]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_3_0_INSERT:%.*]] = insertvalue { i32, i8, i8, { i8, i16 } } [[VAL_FCA_2_INSERT]], i8 [[VAL_FCA_3_0_LOAD]], 3, 0, !dbg [[DBG121]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_3_1_GEP:%.*]] = getelementptr inbounds { i32, i8, i8, { i8, i16 } }, ptr [[PTR]], i32 0, i32 3, i32 1, !dbg [[DBG121]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_3_1_LOAD:%.*]] = load i16, ptr [[VAL_FCA_3_1_GEP]], align 2, !dbg [[DBG121]]
+; CHECK-DEBUGLOC-NEXT: [[VAL_FCA_3_1_INSERT:%.*]] = insertvalue { i32, i8, i8, { i8, i16 } } [[VAL_FCA_3_0_INSERT]], i16 [[VAL_FCA_3_1_LOAD]], 3, 1, !dbg [[DBG121]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata { i32, i8, i8, { i8, i16 } } [[VAL_FCA_3_1_INSERT]], metadata [[META117:![0-9]+]], metadata !DIExpression()), !dbg [[DBG121]]
+; CHECK-DEBUGLOC-NEXT: ret void, !dbg [[DBG122:![0-9]+]]
;
-
%ptr = alloca {i32, i8, i8, {i8, i16}}, align 2
call void @populate(ptr %ptr)
%val = load {i32, i8, i8, {i8, i16}}, ptr %ptr, align 2
@@ -439,17 +438,16 @@ define dso_local i32 @pr45010(ptr %A) {
; CHECK-NEXT: [[B_SROA_0_0_B_SROA_0_0_X:%.*]] = load atomic volatile i32, ptr [[B_SROA_0]] acquire, align 4
; CHECK-NEXT: ret i32 [[B_SROA_0_0_B_SROA_0_0_X]]
;
-; DEBUGLOC-LABEL: @pr45010(
-; DEBUGLOC-NEXT: [[B_SROA_0:%.*]] = alloca i32, align 4, !dbg [[DBG129:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META125:![0-9]+]], metadata !DIExpression()), !dbg [[DBG129]]
-; DEBUGLOC-NEXT: [[TMP1:%.*]] = load i32, ptr [[A:%.*]], align 4, !dbg [[DBG130:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata i32 [[TMP1]], metadata [[META126:![0-9]+]], metadata !DIExpression()), !dbg [[DBG130]]
-; DEBUGLOC-NEXT: store atomic volatile i32 [[TMP1]], ptr [[B_SROA_0]] release, align 4, !dbg [[DBG131:![0-9]+]]
-; DEBUGLOC-NEXT: [[B_SROA_0_0_B_SROA_0_0_X:%.*]] = load atomic volatile i32, ptr [[B_SROA_0]] acquire, align 4, !dbg [[DBG132:![0-9]+]]
-; DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata i32 [[B_SROA_0_0_B_SROA_0_0_X]], metadata [[META128:![0-9]+]], metadata !DIExpression()), !dbg [[DBG132]]
-; DEBUGLOC-NEXT: ret i32 [[B_SROA_0_0_B_SROA_0_0_X]], !dbg [[DBG133:![0-9]+]]
+; CHECK-DEBUGLOC-LABEL: @pr45010(
+; CHECK-DEBUGLOC-NEXT: [[B_SROA_0:%.*]] = alloca i32, align 4, !dbg [[DBG129:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata ptr undef, metadata [[META125:![0-9]+]], metadata !DIExpression()), !dbg [[DBG129]]
+; CHECK-DEBUGLOC-NEXT: [[TMP1:%.*]] = load i32, ptr [[A:%.*]], align 4, !dbg [[DBG130:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata i32 [[TMP1]], metadata [[META126:![0-9]+]], metadata !DIExpression()), !dbg [[DBG130]]
+; CHECK-DEBUGLOC-NEXT: store atomic volatile i32 [[TMP1]], ptr [[B_SROA_0]] release, align 4, !dbg [[DBG131:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: [[B_SROA_0_0_B_SROA_0_0_X:%.*]] = load atomic volatile i32, ptr [[B_SROA_0]] acquire, align 4, !dbg [[DBG132:![0-9]+]]
+; CHECK-DEBUGLOC-NEXT: call void @llvm.dbg.value(metadata i32 [[B_SROA_0_0_B_SROA_0_0_X]], metadata [[META128:![0-9]+]], metadata !DIExpression()), !dbg [[DBG132]]
+; CHECK-DEBUGLOC-NEXT: ret i32 [[B_SROA_0_0_B_SROA_0_0_X]], !dbg [[DBG133:![0-9]+]]
;
-
%B = alloca %struct, align 4
%1 = load i32, ptr %A, align 4
store atomic volatile i32 %1, ptr %B release, align 4
diff --git a/llvm/test/Transforms/SROA/basictest.ll b/llvm/test/Transforms/SROA/basictest.ll
index 5ac8ed8c6e6a..6ea676ca1d09 100644
--- a/llvm/test/Transforms/SROA/basictest.ll
+++ b/llvm/test/Transforms/SROA/basictest.ll
@@ -13,7 +13,6 @@ define i32 @test0() {
; CHECK-NEXT: [[SUM1:%.*]] = add i32 0, [[V2_INT]]
; CHECK-NEXT: ret i32 [[SUM1]]
;
-
entry:
%a1 = alloca i32
%a2 = alloca float
@@ -42,7 +41,6 @@ define i32 @test1() {
; CHECK-NEXT: entry:
; CHECK-NEXT: ret i32 0
;
-
entry:
%X = alloca { i32, float }
%Y = getelementptr { i32, float }, ptr %X, i64 0, i32 0
@@ -58,7 +56,6 @@ define i64 @test2(i64 %X) {
; CHECK: L2:
; CHECK-NEXT: ret i64 [[X:%.*]]
;
-
entry:
%A = alloca [8 x i8]
store i64 %X, ptr %A
@@ -76,7 +73,6 @@ define i64 @test2_addrspacecast(i64 %X) {
; CHECK: L2:
; CHECK-NEXT: ret i64 [[X:%.*]]
;
-
entry:
%A = alloca [8 x i8]
%B = addrspacecast ptr %A to ptr addrspace(1)
@@ -95,7 +91,6 @@ define i64 @test2_addrspacecast_gep(i64 %X, i16 %idx) {
; CHECK: L2:
; CHECK-NEXT: ret i64 [[X:%.*]]
;
-
entry:
%A = alloca [256 x i8]
%B = addrspacecast ptr %A to ptr addrspace(1)
@@ -122,7 +117,6 @@ define i64 @test2_addrspacecast_gep_offset(i64 %X) {
; CHECK-NEXT: [[A_SROA_0_0_A_SROA_0_30_Z:%.*]] = load i64, ptr [[A_SROA_0]], align 1
; CHECK-NEXT: ret i64 [[A_SROA_0_0_A_SROA_0_30_Z]]
;
-
entry:
%A = alloca [256 x i8]
%B = addrspacecast ptr %A to ptr addrspace(1)
@@ -235,7 +229,6 @@ define void @test3(ptr %dst, ptr align 8 %src) {
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[A_SROA_31_0_DST_SROA_IDX]], ptr align 1 [[A_SROA_31]], i32 85, i1 false), !tbaa [[TBAA59]]
; CHECK-NEXT: ret void
;
-
entry:
%a = alloca [300 x i8]
@@ -371,7 +364,6 @@ define void @test4(ptr %dst, ptr %src) {
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[A_SROA_7_0_DST_SROA_IDX]], ptr align 1 [[A_SROA_7]], i32 40, i1 false), !tbaa [[TBAA7]]
; CHECK-NEXT: ret void
;
-
entry:
%a = alloca [100 x i8]
@@ -406,7 +398,6 @@ define i16 @test5() {
; CHECK-NEXT: [[A_SROA_0_2_EXTRACT_TRUNC:%.*]] = trunc i32 [[A_SROA_0_2_EXTRACT_SHIFT]] to i16
; CHECK-NEXT: ret i16 [[A_SROA_0_2_EXTRACT_TRUNC]]
;
-
entry:
%a = alloca [4 x i8]
store float 0.0, ptr %a
@@ -423,7 +414,6 @@ define i16 @test5_multi_addrspace_access() {
; CHECK-NEXT: [[A_SROA_0_2_EXTRACT_TRUNC:%.*]] = trunc i32 [[A_SROA_0_2_EXTRACT_SHIFT]] to i16
; CHECK-NEXT: ret i16 [[A_SROA_0_2_EXTRACT_TRUNC]]
;
-
entry:
%a = alloca [4 x i8]
%fptr.as1 = addrspacecast ptr %a to ptr addrspace(1)
@@ -441,7 +431,6 @@ define i32 @test6() {
; CHECK-NEXT: [[A_SROA_0_0_A_SROA_0_0_VAL:%.*]] = load i32, ptr [[A_SROA_0]], align 4
; CHECK-NEXT: ret i32 [[A_SROA_0_0_A_SROA_0_0_VAL]]
;
-
entry:
%a = alloca [4 x i8]
call void @llvm.memset.p0.i32(ptr %a, i8 42, i32 4, i1 true)
@@ -459,7 +448,6 @@ define void @test7(ptr %src, ptr %dst) {
; CHECK-NEXT: store volatile i32 [[A_SROA_0_0_A_SROA_0_0_COPYLOAD1]], ptr [[DST:%.*]], align 1, !tbaa [[TBAA3]]
; CHECK-NEXT: ret void
;
-
entry:
%a = alloca [4 x i8]
call void @llvm.memcpy.p0.p0.i32(ptr %a, ptr %src, i32 4, i1 true), !tbaa !0
@@ -508,6 +496,7 @@ define i64 @test9() {
; weird bit casts and types. This is valid IR due to the alignment and masking
; off the bits past the end of the alloca.
;
+;
; CHECK-LABEL: @test9(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_3_0_INSERT_EXT:%.*]] = zext i8 26 to i64
@@ -524,7 +513,6 @@ define i64 @test9() {
; CHECK-NEXT: [[RESULT:%.*]] = and i64 [[A_SROA_0_0_INSERT_INSERT]], 16777215
; CHECK-NEXT: ret i64 [[RESULT]]
;
-
entry:
%a = alloca { [3 x i8] }, align 8
store i8 0, ptr %a, align 1
@@ -543,7 +531,6 @@ define ptr @test10() {
; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr null to i64
; CHECK-NEXT: ret ptr null
;
-
entry:
%a = alloca [8 x i8]
call void @llvm.memset.p0.i32(ptr %a, i8 0, i32 8, i1 false)
@@ -560,7 +547,6 @@ define i32 @test11(i1 %c1) {
; CHECK: bad:
; CHECK-NEXT: ret i32 poison
;
-
entry:
%X = alloca i32
br i1 %c1, label %good, label %bad
@@ -581,6 +567,7 @@ define i8 @test12() {
; We fully promote these to the i24 load or store size, resulting in just masks
; and other operations that instcombine will fold, but no alloca.
;
+;
; CHECK-LABEL: @test12(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_3_0_INSERT_EXT:%.*]] = zext i8 0 to i24
@@ -603,7 +590,6 @@ define i8 @test12() {
; CHECK-NEXT: [[BSUM1:%.*]] = add i8 [[BSUM0]], [[B_SROA_3_0_EXTRACT_TRUNC]]
; CHECK-NEXT: ret i8 [[BSUM1]]
;
-
entry:
%a = alloca [3 x i8]
%b = alloca [3 x i8]
@@ -630,13 +616,13 @@ entry:
define i32 @test13() {
; Ensure we don't crash and handle undefined loads that straddle the end of the
; allocation.
+;
; CHECK-LABEL: @test13(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_2_2_LOAD_EXT:%.*]] = zext i8 0 to i16
; CHECK-NEXT: [[RET:%.*]] = zext i16 [[A_SROA_2_2_LOAD_EXT]] to i32
; CHECK-NEXT: ret i32 [[RET]]
;
-
entry:
%a = alloca [3 x i8], align 2
store i8 0, ptr %a
@@ -657,11 +643,11 @@ define void @test14(...) nounwind uwtable {
; also gain enough data to prove they must be dead allocas due to GEPs that walk
; across two adjacent allocas. Test that we don't try to promote or otherwise
; do bad things to these dead allocas, they should just be removed.
+;
; CHECK-LABEL: @test14(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret void
;
-
entry:
%a = alloca %test14.struct
%p = alloca ptr
@@ -683,13 +669,13 @@ define i32 @test15(i1 %flag) nounwind uwtable {
; Ensure that when there are dead instructions using an alloca that are not
; loads or stores we still delete them during partitioning and rewriting.
; Otherwise we'll go to promote them while thy still have unpromotable uses.
+;
; CHECK-LABEL: @test15(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: br label [[LOOP]]
;
-
entry:
%l0 = alloca i64
%l1 = alloca i64
@@ -722,13 +708,13 @@ loop:
define void @test16(ptr %src, ptr %dst) {
; Ensure that we can promote an alloca of [3 x i8] to an i24 SSA value.
+;
; CHECK-LABEL: @test16(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0_0_COPYLOAD:%.*]] = load i24, ptr [[SRC:%.*]], align 1, !tbaa [[TBAA0]]
; CHECK-NEXT: store i24 0, ptr [[DST:%.*]], align 1, !tbaa [[TBAA5]]
; CHECK-NEXT: ret void
;
-
entry:
%a = alloca [3 x i8]
call void @llvm.memcpy.p0.p0.i32(ptr %a, ptr %src, i32 4, i1 false), !tbaa !0
@@ -740,6 +726,7 @@ entry:
define void @test17(ptr %src, ptr %dst) {
; Ensure that we can rewrite unpromotable memcpys which extend past the end of
; the alloca.
+;
; CHECK-LABEL: @test17(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A:%.*]] = alloca [3 x i8], align 1
@@ -747,7 +734,6 @@ define void @test17(ptr %src, ptr %dst) {
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr [[DST:%.*]], ptr [[A]], i32 4, i1 true), !tbaa [[TBAA3]]
; CHECK-NEXT: ret void
;
-
entry:
%a = alloca [3 x i8]
call void @llvm.memcpy.p0.p0.i32(ptr %a, ptr %src, i32 4, i1 true), !tbaa !0
@@ -759,6 +745,7 @@ define void @test18(ptr %src, ptr %dst, i32 %size) {
; Preserve transfer intrinsics with a variable size, even if they overlap with
; fixed size operations. Further, continue to split and promote allocas preceding
; the variable sized intrinsic.
+;
; CHECK-LABEL: @test18(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_33:%.*]] = alloca [34 x i8], align 1
@@ -773,7 +760,6 @@ define void @test18(ptr %src, ptr %dst, i32 %size) {
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr [[DST]], ptr align 1 [[A_SROA_33]], i32 [[SIZE]], i1 false), !tbaa [[TBAA11]]
; CHECK-NEXT: ret void
;
-
entry:
%a = alloca [42 x i8]
call void @llvm.memcpy.p0.p0.i32(ptr %a, ptr %src, i32 8, i1 false), !tbaa !0
@@ -793,6 +779,7 @@ define i64 @test19(ptr %x) {
; pointers in such a way that we try to GEP through the opaque type. Previously,
; a check for an unsized type was missing and this crashed. Ensure it behaves
; reasonably now.
+;
; CHECK-LABEL: @test19(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0_0_COPYLOAD:%.*]] = load i64, ptr [[X:%.*]], align 1
@@ -800,7 +787,6 @@ define i64 @test19(ptr %x) {
; CHECK-NEXT: [[A_SROA_2_0_COPYLOAD:%.*]] = load ptr, ptr [[A_SROA_2_0_X_SROA_IDX]], align 1
; CHECK-NEXT: ret i64 [[A_SROA_0_0_COPYLOAD]]
;
-
entry:
%a = alloca { i64, ptr }
call void @llvm.memcpy.p0.p0.i32(ptr %a, ptr %x, i32 16, i1 false)
@@ -816,6 +802,7 @@ define i64 @test19_addrspacecast(ptr %x) {
; pointers in such a way that we try to GEP through the opaque type. Previously,
; a check for an unsized type was missing and this crashed. Ensure it behaves
; reasonably now.
+;
; CHECK-LABEL: @test19_addrspacecast(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CAST1:%.*]] = addrspacecast ptr [[X:%.*]] to ptr addrspace(1)
@@ -824,7 +811,6 @@ define i64 @test19_addrspacecast(ptr %x) {
; CHECK-NEXT: [[A_SROA_2_0_COPYLOAD:%.*]] = load ptr, ptr addrspace(1) [[A_SROA_2_0_CAST1_SROA_IDX]], align 1
; CHECK-NEXT: ret i64 [[A_SROA_0_0_COPYLOAD]]
;
-
entry:
%a = alloca { i64, ptr }
%cast1 = addrspacecast ptr %x to ptr addrspace(1)
@@ -837,13 +823,13 @@ entry:
define i32 @test20() {
; Ensure we can track negative offsets (before the beginning of the alloca) and
; negative relative offsets from offsets starting past the end of the alloca.
+;
; CHECK-LABEL: @test20(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[SUM1:%.*]] = add i32 1, 2
; CHECK-NEXT: [[SUM2:%.*]] = add i32 [[SUM1]], 3
; CHECK-NEXT: ret i32 [[SUM2]]
;
-
entry:
%a = alloca [3 x i32]
store i32 1, ptr %a
@@ -868,12 +854,12 @@ define i8 @test21() {
; Test allocations and offsets which border on overflow of the int64_t used
; internally. This is really awkward to really test as LLVM doesn't really
; support such extreme constructs cleanly.
+;
; CHECK-LABEL: @test21(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[RESULT:%.*]] = or i8 -1, -1
; CHECK-NEXT: ret i8 [[RESULT]]
;
-
entry:
%a = alloca [2305843009213693951 x i8]
%gep0 = getelementptr [2305843009213693951 x i8], ptr %a, i64 0, i64 2305843009213693949
@@ -898,11 +884,11 @@ entry:
define void @PR13916.1() {
; Ensure that we handle overlapping memcpy intrinsics correctly, especially in
; the case where there is a directly identical value for both source and dest.
+;
; CHECK-LABEL: @PR13916.1(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret void
;
-
entry:
%a = alloca i8
call void @llvm.memcpy.p0.p0.i32(ptr %a, ptr %a, i32 1, i1 false)
@@ -914,6 +900,7 @@ define void @PR13916.2(i1 %c1) {
; Check whether we continue to handle them correctly when they start off with
;
diff erent pointer value chains, but during rewriting we coalesce them into the
; same value.
+;
; CHECK-LABEL: @PR13916.2(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[C1:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
@@ -922,7 +909,6 @@ define void @PR13916.2(i1 %c1) {
; CHECK: if.end:
; CHECK-NEXT: ret void
;
-
entry:
%a = alloca %PR13916.struct, align 1
br i1 %c1, label %if.then, label %if.end
@@ -940,6 +926,7 @@ define void @PR13990(i1 %c1, i1 %c2, i1 %c3, i1 %c4, ptr %ptr) {
; Ensure we can handle cases where processing one alloca causes the other
; alloca to become dead and get deleted. This might crash or fail under
; Valgrind if we regress.
+;
; CHECK-LABEL: @PR13990(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
@@ -952,7 +939,6 @@ define void @PR13990(i1 %c1, i1 %c2, i1 %c3, i1 %c4, ptr %ptr) {
; CHECK: bb4:
; CHECK-NEXT: unreachable
;
-
entry:
%tmp1 = alloca ptr
%tmp2 = alloca ptr
@@ -977,11 +963,11 @@ define double @PR13969(double %x) {
; Check that we detect when promotion will un-escape an alloca and iterate to
; re-try running SROA over that alloca. Without that, the two allocas that are
; stored into a dead alloca don't get rewritten and promoted.
+;
; CHECK-LABEL: @PR13969(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret double [[X:%.*]]
;
-
entry:
%a = alloca double
%b = alloca ptr
@@ -1003,13 +989,13 @@ define void @PR14034(ptr %ptr, ptr %ptr2) {
; This test case tries to form GEPs into the empty leading struct members, and
; subsequently crashed (under valgrind) before we fixed the PR. The important
; thing is to handle empty structs gracefully.
+;
; CHECK-LABEL: @PR14034(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca [12 x i8], align 8
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[PTR2:%.*]], ptr align 8 [[A_SROA_0]], i32 12, i1 false)
; CHECK-NEXT: ret void
;
-
entry:
%a = alloca %PR14034.struct
%list = getelementptr %PR14034.struct, ptr %a, i32 0, i32 2
@@ -1022,6 +1008,7 @@ entry:
define i32 @test22(i32 %x) {
; Test that SROA and promotion is not confused by a grab bax mixture of pointer
; types involving wrapper aggregates and zero-length aggregate members.
+;
; CHECK-LABEL: @test22(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[WRAP1:%.*]] = insertvalue [1 x { i32 }] poison, i32 [[X:%.*]], 0, 0
@@ -1043,7 +1030,6 @@ define i32 @test22(i32 %x) {
; CHECK-NEXT: [[VALCAST2:%.*]] = bitcast float [[UNWRAP2]] to i32
; CHECK-NEXT: ret i32 [[VALCAST2]]
;
-
entry:
%a1 = alloca { { [1 x { i32 }] } }
%a2 = alloca { {}, { float }, [0 x i8] }
@@ -1085,6 +1071,7 @@ define void @PR14059.1(ptr %d) {
; whole-alloca operations, and perform the appropriate bitcasting on the
; *values* rather than the pointers. When this works, partial reads and writes
; via integers can be promoted away.
+;
; CHECK-LABEL: @PR14059.1(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = bitcast double undef to i64
@@ -1112,7 +1099,6 @@ define void @PR14059.1(ptr %d) {
; CHECK-NEXT: store double [[ADD_R_I]], ptr [[D]], align 8
; CHECK-NEXT: ret void
;
-
entry:
%X.sroa.0.i = alloca double, align 8
call void @llvm.lifetime.start.p0(i64 -1, ptr %X.sroa.0.i)
@@ -1148,6 +1134,7 @@ define i64 @PR14059.2(ptr %phi) {
; underlying alloca has smaller components that are accessed independently. This
; shows up particularly with ABI lowering patterns coming out of Clang that rely
; on the particular register placement of a single large integer return value.
+;
; CHECK-LABEL: @PR14059.2(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[PHI_REALP:%.*]] = getelementptr inbounds { float, float }, ptr [[PHI:%.*]], i32 0, i32 0
@@ -1165,7 +1152,6 @@ define i64 @PR14059.2(ptr %phi) {
; CHECK-NEXT: [[RETVAL_SROA_0_0_INSERT_INSERT:%.*]] = or i64 [[RETVAL_SROA_0_0_INSERT_MASK]], [[RETVAL_SROA_0_0_INSERT_EXT]]
; CHECK-NEXT: ret i64 [[RETVAL_SROA_0_0_INSERT_INSERT]]
;
-
entry:
%retval = alloca { float, float }, align 4
@@ -1189,6 +1175,7 @@ define void @PR14105(ptr %ptr) {
; Ensure that when rewriting the GEP index '-1' for this alloca we preserve is
; sign as negative. We use a volatile memcpy to ensure promotion never actually
; occurs.
+;
; CHECK-LABEL: @PR14105(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca [16 x i8], align 8
@@ -1196,7 +1183,6 @@ define void @PR14105(ptr %ptr) {
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[GEP]], ptr align 8 [[A_SROA_0]], i32 16, i1 true)
; CHECK-NEXT: ret void
;
-
entry:
%a = alloca { [16 x i8] }, align 8
@@ -1208,6 +1194,7 @@ entry:
define void @PR14105_as1(ptr addrspace(1) %ptr) {
; Make sure this the right address space pointer is used for type check.
+;
; CHECK-LABEL: @PR14105_as1(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A:%.*]] = alloca { [16 x i8] }, align 8
@@ -1215,7 +1202,6 @@ define void @PR14105_as1(ptr addrspace(1) %ptr) {
; CHECK-NEXT: call void @llvm.memcpy.p1.p0.i32(ptr addrspace(1) align 8 [[GEP]], ptr align 8 [[A]], i32 16, i1 true)
; CHECK-NEXT: ret void
;
-
entry:
%a = alloca { [16 x i8] }, align 8
%gep = getelementptr inbounds { [16 x i8] }, ptr addrspace(1) %ptr, i64 -1
@@ -1226,12 +1212,12 @@ entry:
define void @PR14465() {
; Ensure that we don't crash when analyzing a alloca larger than the maximum
; integer type width (MAX_INT_BITS) supported by llvm (1048576*32 > (1<<23)-1).
+;
; CHECK-LABEL: @PR14465(
; CHECK-NEXT: [[STACK:%.*]] = alloca [1048576 x i32], align 16
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[STACK]], i8 -2, i64 4194304, i1 false)
; CHECK-NEXT: ret void
;
-
%stack = alloca [1048576 x i32], align 16
call void @llvm.memset.p0.i64(ptr align 16 %stack, i8 -2, i64 4194304, i1 false)
ret void
@@ -1244,6 +1230,7 @@ define void @PR14548(i1 %x) {
; iteratively.
; Note that we don't do a particularly good *job* of handling these mixtures,
; but the hope is that this is very rare.
+;
; CHECK-LABEL: @PR14548(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca i8, align 8
@@ -1256,7 +1243,6 @@ define void @PR14548(i1 %x) {
; CHECK-NEXT: [[A_SROA_0_0_A_SROA_0_0_BAZ:%.*]] = load i1, ptr [[A_SROA_0]], align 8
; CHECK-NEXT: ret void
;
-
entry:
%a = alloca <{ i1 }>, align 8
%b = alloca <{ i1 }>, align 8
@@ -1274,6 +1260,7 @@ entry:
define <3 x i8> @PR14572.1(i32 %x) {
; Ensure that a split integer store which is wider than the type size of the
; alloca (relying on the alloc size padding) doesn't trigger an assert.
+;
; CHECK-LABEL: @PR14572.1(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[X:%.*]] to i24
@@ -1282,7 +1269,6 @@ define <3 x i8> @PR14572.1(i32 %x) {
; CHECK-NEXT: [[A_SROA_2_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[A_SROA_2_0_EXTRACT_SHIFT]] to i8
; CHECK-NEXT: ret <3 x i8> [[TMP0]]
;
-
entry:
%a = alloca <3 x i8>, align 4
@@ -1294,6 +1280,7 @@ entry:
define i32 @PR14572.2(<3 x i8> %x) {
; Ensure that a split integer load which is wider than the type size of the
; alloca (relying on the alloc size padding) doesn't trigger an assert.
+;
; CHECK-LABEL: @PR14572.2(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <3 x i8> [[X:%.*]] to i24
@@ -1306,7 +1293,6 @@ define i32 @PR14572.2(<3 x i8> %x) {
; CHECK-NEXT: [[A_0_INSERT_INSERT:%.*]] = or i32 [[A_0_INSERT_MASK]], [[A_0_INSERT_EXT]]
; CHECK-NEXT: ret i32 [[A_0_INSERT_INSERT]]
;
-
entry:
%a = alloca <3 x i8>, align 4
@@ -1318,6 +1304,7 @@ entry:
define i32 @PR14601(i32 %x) {
; Don't try to form a promotable integer alloca when there is a variable length
; memory intrinsic.
+;
; CHECK-LABEL: @PR14601(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
@@ -1325,7 +1312,6 @@ define i32 @PR14601(i32 %x) {
; CHECK-NEXT: [[A_0_V:%.*]] = load i32, ptr [[A]], align 4
; CHECK-NEXT: ret i32 [[A_0_V]]
;
-
entry:
%a = alloca i32
@@ -1340,6 +1326,7 @@ define void @PR15674(ptr %data, ptr %src, i32 %size) {
; beginning of the array. Ensure that the final integer store, despite being
; convertable to the integer type that we end up promoting this alloca toward,
; doesn't get widened to a full alloca store.
+;
; CHECK-LABEL: @PR15674(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP_SROA_0:%.*]] = alloca i32, align 4
@@ -1375,7 +1362,6 @@ define void @PR15674(ptr %data, ptr %src, i32 %size) {
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr [[DATA:%.*]], ptr align 4 [[TMP_SROA_0]], i32 [[SIZE]], i1 false)
; CHECK-NEXT: ret void
;
-
entry:
%tmp = alloca [4 x i8], align 1
@@ -1426,7 +1412,6 @@ define void @PR15805(i1 %a, i1 %b) {
; CHECK-NEXT: [[COND_SROA_SPECULATED:%.*]] = select i1 [[B:%.*]], i64 undef, i64 undef
; CHECK-NEXT: ret void
;
-
%c = alloca i64, align 8
%p.0.c = select i1 %a, ptr %c, ptr %c
%cond.in = select i1 %b, ptr %p.0.c, ptr %c
@@ -1439,6 +1424,7 @@ define void @PR15805.1(i1 %a, i1 %b, i1 %c2) {
; of looping unreachable code. This helps ensure that we aren't sensitive to the
; order in which the uses of the alloca are visited.
;
+;
; CHECK-LABEL: @PR15805.1(
; CHECK-NEXT: br label [[EXIT:%.*]]
; CHECK: loop:
@@ -1447,7 +1433,6 @@ define void @PR15805.1(i1 %a, i1 %b, i1 %c2) {
; CHECK: exit:
; CHECK-NEXT: ret void
;
-
%c = alloca i64, align 8
br label %exit
@@ -1466,6 +1451,7 @@ define void @PR16651.1(ptr %a) {
; lowering to integer loads and stores of a width other than that of the original
; memcpy.
;
+;
; CHECK-LABEL: @PR16651.1(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[B_SROA_0:%.*]] = alloca i16, align 4
@@ -1482,7 +1468,6 @@ define void @PR16651.1(ptr %a) {
; CHECK-NEXT: [[B_SROA_1_0_B_SROA_1_2_:%.*]] = load i8, ptr [[B_SROA_1]], align 2
; CHECK-NEXT: unreachable
;
-
entry:
%b = alloca i32, align 4
call void @llvm.memcpy.p0.p0.i32(ptr align 4 %b, ptr align 4 %a, i32 4, i1 true)
@@ -1497,6 +1482,7 @@ define void @PR16651.2(<2 x float> %val, i1 %c1) {
; analyzing whether we could form a vector promotion because that code didn't
; bail on select instructions.
;
+;
; CHECK-LABEL: @PR16651.2(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TV1_SROA_0:%.*]] = alloca <2 x float>, align 8
@@ -1505,7 +1491,6 @@ define void @PR16651.2(<2 x float> %val, i1 %c1) {
; CHECK-NEXT: [[COND105_I_I:%.*]] = load float, ptr [[COND105_IN_I_I]], align 8
; CHECK-NEXT: ret void
;
-
entry:
%tv1 = alloca { <2 x float>, <2 x float> }, align 8
%0 = getelementptr { <2 x float>, <2 x float> }, ptr %tv1, i64 0, i32 1
@@ -1551,7 +1536,6 @@ define void @test24(ptr %src, ptr %dst) {
; CHECK-NEXT: store volatile i64 [[A_0_COPYLOAD1]], ptr [[DST:%.*]], align 1, !tbaa [[TBAA3]]
; CHECK-NEXT: ret void
;
-
entry:
%a = alloca i64, align 16
call void @llvm.memcpy.p0.p0.i32(ptr %a, ptr %src, i32 8, i1 true), !tbaa !0
@@ -1567,6 +1551,7 @@ define float @test25() {
; an integer load and store. SROA needs to be extremely powerful to correctly
; handle these cases and form splitable and promotable SSA values.
;
+;
; CHECK-LABEL: @test25(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 0 to float
@@ -1574,7 +1559,6 @@ define float @test25() {
; CHECK-NEXT: [[RET:%.*]] = fadd float [[TMP0]], [[TMP1]]
; CHECK-NEXT: ret float [[RET]]
;
-
entry:
%a = alloca i64
%b = alloca i64
@@ -1596,6 +1580,7 @@ entry:
define void @test26() {
; Test a case of splitting up loads and stores against a globals.
;
+;
; CHECK-LABEL: @test26(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[V13:%.*]] = load i32, ptr @complex1, align 4
@@ -1609,7 +1594,6 @@ define void @test26() {
; CHECK-NEXT: store i32 [[TMP3]], ptr getelementptr inbounds (i8, ptr @complex2, i64 4), align 4
; CHECK-NEXT: ret void
;
-
entry:
%a = alloca i64
%a.gep2 = getelementptr [2 x float], ptr %a, i32 0, i32 1
@@ -1630,6 +1614,7 @@ define float @test27() {
; is a particularly challenging one because the load and store both point into
; the alloca SROA is processing, and they overlap but at an offset.
;
+;
; CHECK-LABEL: @test27(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 0 to float
@@ -1637,7 +1622,6 @@ define float @test27() {
; CHECK-NEXT: [[RET:%.*]] = fadd float [[TMP0]], [[TMP1]]
; CHECK-NEXT: ret float [[RET]]
;
-
entry:
%a = alloca [12 x i8]
%gep2 = getelementptr [12 x i8], ptr %a, i32 0, i32 4
@@ -1660,6 +1644,7 @@ define i32 @PR22093() {
; this alloca we need to handle it specially to ensure the splits line up
; properly for rewriting.
;
+;
; CHECK-LABEL: @PR22093(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca i16, align 4
@@ -1678,7 +1663,6 @@ define i32 @PR22093() {
; CHECK-NEXT: [[A_SROA_3_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[A_SROA_3_0_EXTRACT_SHIFT]] to i16
; CHECK-NEXT: ret i32 [[A_SROA_0_0_INSERT_INSERT]]
;
-
entry:
%a = alloca i32
store volatile i16 42, ptr %a
@@ -1696,6 +1680,7 @@ define void @PR22093.2() {
; remove the first store from the presplit candidates as its load won't be
; presplit.
;
+;
; CHECK-LABEL: @PR22093.2(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca i16, align 8
@@ -1720,7 +1705,6 @@ define void @PR22093.2() {
; CHECK-NEXT: [[A_SROA_5_4_EXTRACT_TRUNC:%.*]] = trunc i32 [[A_SROA_5_4_EXTRACT_SHIFT]] to i24
; CHECK-NEXT: ret void
;
-
entry:
%a = alloca i64
store volatile i16 42, ptr %a
@@ -1753,6 +1737,7 @@ define i16 @PR24463() {
; a sub-integer that requires extraction *and* extends past the end of the
; alloca. SROA can split the alloca to avoid shift or trunc.
;
+;
; CHECK-LABEL: @PR24463(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ALLOCA_SROA_1_2_LOAD_EXT:%.*]] = zext i8 0 to i16
@@ -1856,6 +1841,7 @@ declare void @callee48(i48 %a)
define void @test28(i64 %v) #0 {
; SROA should split the first i64 store to avoid additional and/or instructions
; when storing into i32 fields
+;
; CHECK-LABEL: @test28(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[T_SROA_0_8_EXTRACT_TRUNC:%.*]] = trunc i64 [[V:%.*]] to i32
@@ -1863,7 +1849,6 @@ define void @test28(i64 %v) #0 {
; CHECK-NEXT: [[T_SROA_2_8_EXTRACT_TRUNC:%.*]] = trunc i64 [[T_SROA_2_8_EXTRACT_SHIFT]] to i32
; CHECK-NEXT: ret void
;
-
entry:
%t = alloca { i64, i32, i32 }
@@ -1907,7 +1892,6 @@ define void @test29(i32 %num, i32 %tid) {
; CHECK: bb7:
; CHECK-NEXT: ret void
;
-
entry:
%ra = alloca [10 x float], align 4
call void @llvm.lifetime.start.isVoid.i64.p0(i64 40, ptr nonnull %ra)
diff --git a/llvm/test/Transforms/SROA/big-endian.ll b/llvm/test/Transforms/SROA/big-endian.ll
index 30edb896697e..c81497f1aca0 100644
--- a/llvm/test/Transforms/SROA/big-endian.ll
+++ b/llvm/test/Transforms/SROA/big-endian.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=sroa -S | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
@@ -9,11 +10,30 @@ define i8 @test1() {
; ordering.
;
; CHECK-LABEL: @test1(
-
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A_SROA_3_0_INSERT_EXT:%.*]] = zext i8 0 to i24
+; CHECK-NEXT: [[A_SROA_3_0_INSERT_MASK:%.*]] = and i24 undef, -256
+; CHECK-NEXT: [[A_SROA_3_0_INSERT_INSERT:%.*]] = or i24 [[A_SROA_3_0_INSERT_MASK]], [[A_SROA_3_0_INSERT_EXT]]
+; CHECK-NEXT: [[A_SROA_2_0_INSERT_EXT:%.*]] = zext i8 0 to i24
+; CHECK-NEXT: [[A_SROA_2_0_INSERT_SHIFT:%.*]] = shl i24 [[A_SROA_2_0_INSERT_EXT]], 8
+; CHECK-NEXT: [[A_SROA_2_0_INSERT_MASK:%.*]] = and i24 [[A_SROA_3_0_INSERT_INSERT]], -65281
+; CHECK-NEXT: [[A_SROA_2_0_INSERT_INSERT:%.*]] = or i24 [[A_SROA_2_0_INSERT_MASK]], [[A_SROA_2_0_INSERT_SHIFT]]
+; CHECK-NEXT: [[A_SROA_0_0_INSERT_EXT:%.*]] = zext i8 0 to i24
+; CHECK-NEXT: [[A_SROA_0_0_INSERT_SHIFT:%.*]] = shl i24 [[A_SROA_0_0_INSERT_EXT]], 16
+; CHECK-NEXT: [[A_SROA_0_0_INSERT_MASK:%.*]] = and i24 [[A_SROA_2_0_INSERT_INSERT]], 65535
+; CHECK-NEXT: [[A_SROA_0_0_INSERT_INSERT:%.*]] = or i24 [[A_SROA_0_0_INSERT_MASK]], [[A_SROA_0_0_INSERT_SHIFT]]
+; CHECK-NEXT: [[B_SROA_0_0_EXTRACT_SHIFT:%.*]] = lshr i24 [[A_SROA_0_0_INSERT_INSERT]], 16
+; CHECK-NEXT: [[B_SROA_0_0_EXTRACT_TRUNC:%.*]] = trunc i24 [[B_SROA_0_0_EXTRACT_SHIFT]] to i8
+; CHECK-NEXT: [[B_SROA_2_0_EXTRACT_SHIFT:%.*]] = lshr i24 [[A_SROA_0_0_INSERT_INSERT]], 8
+; CHECK-NEXT: [[B_SROA_2_0_EXTRACT_TRUNC:%.*]] = trunc i24 [[B_SROA_2_0_EXTRACT_SHIFT]] to i8
+; CHECK-NEXT: [[B_SROA_3_0_EXTRACT_TRUNC:%.*]] = trunc i24 [[A_SROA_0_0_INSERT_INSERT]] to i8
+; CHECK-NEXT: [[BSUM0:%.*]] = add i8 [[B_SROA_0_0_EXTRACT_TRUNC]], [[B_SROA_2_0_EXTRACT_TRUNC]]
+; CHECK-NEXT: [[BSUM1:%.*]] = add i8 [[BSUM0]], [[B_SROA_3_0_EXTRACT_TRUNC]]
+; CHECK-NEXT: ret i8 [[BSUM1]]
+;
entry:
%a = alloca [3 x i8]
%b = alloca [3 x i8]
-; CHECK-NOT: alloca
store i8 0, ptr %a
%a1ptr = getelementptr [3 x i8], ptr %a, i64 0, i32 1
@@ -21,19 +41,6 @@ entry:
%a2ptr = getelementptr [3 x i8], ptr %a, i64 0, i32 2
store i8 0, ptr %a2ptr
%ai = load i24, ptr %a
-; CHECK-NOT: store
-; CHECK-NOT: load
-; CHECK: %[[ext2:.*]] = zext i8 0 to i24
-; CHECK-NEXT: %[[mask2:.*]] = and i24 undef, -256
-; CHECK-NEXT: %[[insert2:.*]] = or i24 %[[mask2]], %[[ext2]]
-; CHECK-NEXT: %[[ext1:.*]] = zext i8 0 to i24
-; CHECK-NEXT: %[[shift1:.*]] = shl i24 %[[ext1]], 8
-; CHECK-NEXT: %[[mask1:.*]] = and i24 %[[insert2]], -65281
-; CHECK-NEXT: %[[insert1:.*]] = or i24 %[[mask1]], %[[shift1]]
-; CHECK-NEXT: %[[ext0:.*]] = zext i8 0 to i24
-; CHECK-NEXT: %[[shift0:.*]] = shl i24 %[[ext0]], 16
-; CHECK-NEXT: %[[mask0:.*]] = and i24 %[[insert1]], 65535
-; CHECK-NEXT: %[[insert0:.*]] = or i24 %[[mask0]], %[[shift0]]
store i24 %ai, ptr %b
%b0 = load i8, ptr %b
@@ -41,20 +48,10 @@ entry:
%b1 = load i8, ptr %b1ptr
%b2ptr = getelementptr [3 x i8], ptr %b, i64 0, i32 2
%b2 = load i8, ptr %b2ptr
-; CHECK-NOT: store
-; CHECK-NOT: load
-; CHECK: %[[shift0:.*]] = lshr i24 %[[insert0]], 16
-; CHECK-NEXT: %[[trunc0:.*]] = trunc i24 %[[shift0]] to i8
-; CHECK-NEXT: %[[shift1:.*]] = lshr i24 %[[insert0]], 8
-; CHECK-NEXT: %[[trunc1:.*]] = trunc i24 %[[shift1]] to i8
-; CHECK-NEXT: %[[trunc2:.*]] = trunc i24 %[[insert0]] to i8
%bsum0 = add i8 %b0, %b1
%bsum1 = add i8 %bsum0, %b2
ret i8 %bsum1
-; CHECK: %[[sum0:.*]] = add i8 %[[trunc0]], %[[trunc1]]
-; CHECK-NEXT: %[[sum1:.*]] = add i8 %[[sum0]], %[[trunc2]]
-; CHECK-NEXT: ret i8 %[[sum1]]
}
define i64 @test2() {
@@ -62,17 +59,35 @@ define i64 @test2() {
; promoted.
;
; CHECK-LABEL: @test2(
-
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A_SROA_2_SROA_4_0_INSERT_EXT:%.*]] = zext i8 1 to i40
+; CHECK-NEXT: [[A_SROA_2_SROA_4_0_INSERT_MASK:%.*]] = and i40 undef, -256
+; CHECK-NEXT: [[A_SROA_2_SROA_4_0_INSERT_INSERT:%.*]] = or i40 [[A_SROA_2_SROA_4_0_INSERT_MASK]], [[A_SROA_2_SROA_4_0_INSERT_EXT]]
+; CHECK-NEXT: [[A_SROA_2_SROA_3_0_INSERT_EXT:%.*]] = zext i24 0 to i40
+; CHECK-NEXT: [[A_SROA_2_SROA_3_0_INSERT_SHIFT:%.*]] = shl i40 [[A_SROA_2_SROA_3_0_INSERT_EXT]], 8
+; CHECK-NEXT: [[A_SROA_2_SROA_3_0_INSERT_MASK:%.*]] = and i40 [[A_SROA_2_SROA_4_0_INSERT_INSERT]], -4294967041
+; CHECK-NEXT: [[A_SROA_2_SROA_3_0_INSERT_INSERT:%.*]] = or i40 [[A_SROA_2_SROA_3_0_INSERT_MASK]], [[A_SROA_2_SROA_3_0_INSERT_SHIFT]]
+; CHECK-NEXT: [[A_SROA_2_SROA_0_0_INSERT_EXT:%.*]] = zext i8 0 to i40
+; CHECK-NEXT: [[A_SROA_2_SROA_0_0_INSERT_SHIFT:%.*]] = shl i40 [[A_SROA_2_SROA_0_0_INSERT_EXT]], 32
+; CHECK-NEXT: [[A_SROA_2_SROA_0_0_INSERT_MASK:%.*]] = and i40 [[A_SROA_2_SROA_3_0_INSERT_INSERT]], 4294967295
+; CHECK-NEXT: [[A_SROA_2_SROA_0_0_INSERT_INSERT:%.*]] = or i40 [[A_SROA_2_SROA_0_0_INSERT_MASK]], [[A_SROA_2_SROA_0_0_INSERT_SHIFT]]
+; CHECK-NEXT: [[A_SROA_2_0_INSERT_EXT:%.*]] = zext i40 [[A_SROA_2_SROA_0_0_INSERT_INSERT]] to i56
+; CHECK-NEXT: [[A_SROA_2_0_INSERT_MASK:%.*]] = and i56 undef, -1099511627776
+; CHECK-NEXT: [[A_SROA_2_0_INSERT_INSERT:%.*]] = or i56 [[A_SROA_2_0_INSERT_MASK]], [[A_SROA_2_0_INSERT_EXT]]
+; CHECK-NEXT: [[A_SROA_0_0_INSERT_EXT:%.*]] = zext i16 1 to i56
+; CHECK-NEXT: [[A_SROA_0_0_INSERT_SHIFT:%.*]] = shl i56 [[A_SROA_0_0_INSERT_EXT]], 40
+; CHECK-NEXT: [[A_SROA_0_0_INSERT_MASK:%.*]] = and i56 [[A_SROA_2_0_INSERT_INSERT]], 1099511627775
+; CHECK-NEXT: [[A_SROA_0_0_INSERT_INSERT:%.*]] = or i56 [[A_SROA_0_0_INSERT_MASK]], [[A_SROA_0_0_INSERT_SHIFT]]
+; CHECK-NEXT: [[RET:%.*]] = zext i56 [[A_SROA_0_0_INSERT_INSERT]] to i64
+; CHECK-NEXT: ret i64 [[RET]]
+;
entry:
%a = alloca [7 x i8]
-; CHECK-NOT: alloca
%a1ptr = getelementptr [7 x i8], ptr %a, i64 0, i32 1
%a2ptr = getelementptr [7 x i8], ptr %a, i64 0, i32 2
%a3ptr = getelementptr [7 x i8], ptr %a, i64 0, i32 3
-; CHECK-NOT: store
-; CHECK-NOT: load
store i16 1, ptr %a
@@ -84,43 +99,20 @@ entry:
; the alloca is splitted into multiple slices
; Here, i8 1 is for %a[6]
-; CHECK: %[[ext1:.*]] = zext i8 1 to i40
-; CHECK-NEXT: %[[mask1:.*]] = and i40 undef, -256
-; CHECK-NEXT: %[[insert1:.*]] = or i40 %[[mask1]], %[[ext1]]
; Here, i24 0 is for %a[3] to %a[5]
-; CHECK-NEXT: %[[ext2:.*]] = zext i24 0 to i40
-; CHECK-NEXT: %[[shift2:.*]] = shl i40 %[[ext2]], 8
-; CHECK-NEXT: %[[mask2:.*]] = and i40 %[[insert1]], -4294967041
-; CHECK-NEXT: %[[insert2:.*]] = or i40 %[[mask2]], %[[shift2]]
; Here, i8 0 is for %a[2]
-; CHECK-NEXT: %[[ext3:.*]] = zext i8 0 to i40
-; CHECK-NEXT: %[[shift3:.*]] = shl i40 %[[ext3]], 32
-; CHECK-NEXT: %[[mask3:.*]] = and i40 %[[insert2]], 4294967295
-; CHECK-NEXT: %[[insert3:.*]] = or i40 %[[mask3]], %[[shift3]]
-; CHECK-NEXT: %[[ext4:.*]] = zext i40 %[[insert3]] to i56
-; CHECK-NEXT: %[[mask4:.*]] = and i56 undef, -1099511627776
-; CHECK-NEXT: %[[insert4:.*]] = or i56 %[[mask4]], %[[ext4]]
-; CHECK-NOT: store
-; CHECK-NOT: load
%ai = load i56, ptr %a
%ret = zext i56 %ai to i64
ret i64 %ret
; Here, i16 1 is for %a[0] to %a[1]
-; CHECK-NEXT: %[[ext5:.*]] = zext i16 1 to i56
-; CHECK-NEXT: %[[shift5:.*]] = shl i56 %[[ext5]], 40
-; CHECK-NEXT: %[[mask5:.*]] = and i56 %[[insert4]], 1099511627775
-; CHECK-NEXT: %[[insert5:.*]] = or i56 %[[mask5]], %[[shift5]]
-; CHECK-NEXT: %[[ret:.*]] = zext i56 %[[insert5]] to i64
-; CHECK-NEXT: ret i64 %[[ret]]
}
define i64 @PR14132(i1 %flag) {
-; CHECK-LABEL: @PR14132(
; Here we form a PHI-node by promoting the pointer alloca first, and then in
; order to promote the other two allocas, we speculate the load of the
; now-phi-node-pointer. In doing so we end up loading a 64-bit value from an i8
@@ -129,11 +121,21 @@ define i64 @PR14132(i1 %flag) {
; steps to only use the not-undef bits, and so we need to at least loosely
; support this. This test is particularly interesting because how we handle
; a load of an i64 from an i8 alloca is dependent on endianness.
+; CHECK-LABEL: @PR14132(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br i1 [[FLAG:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: [[B_0_LOAD_EXT:%.*]] = zext i8 1 to i64
+; CHECK-NEXT: [[B_0_ENDIAN_SHIFT:%.*]] = shl i64 [[B_0_LOAD_EXT]], 56
+; CHECK-NEXT: br label [[IF_END]]
+; CHECK: if.end:
+; CHECK-NEXT: [[PTR_0_SROA_SPECULATED:%.*]] = phi i64 [ [[B_0_ENDIAN_SHIFT]], [[IF_THEN]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: ret i64 [[PTR_0_SROA_SPECULATED]]
+;
entry:
%a = alloca i64, align 8
%b = alloca i8, align 8
%ptr = alloca ptr, align 8
-; CHECK-NOT: alloca
store i64 0, ptr %a
store i8 1, ptr %b
@@ -143,25 +145,17 @@ entry:
if.then:
store ptr %b, ptr %ptr
br label %if.end
-; CHECK-NOT: store
-; CHECK: %[[ext:.*]] = zext i8 1 to i64
-; CHECK: %[[shift:.*]] = shl i64 %[[ext]], 56
if.end:
%tmp = load ptr, ptr %ptr
%result = load i64, ptr %tmp
-; CHECK-NOT: load
-; CHECK: %[[result:.*]] = phi i64 [ %[[shift]], %if.then ], [ 0, %entry ]
ret i64 %result
-; CHECK-NEXT: ret i64 %[[result]]
}
declare void @f(i64 %x, i32 %y)
define void @test3() {
-; CHECK-LABEL: @test3(
-;
; This is a test that specifically exercises the big-endian lowering because it
; ends up splitting a 64-bit integer into two smaller integers and has a number
; of tricky aspects (the i24 type) that make that hard. Historically, SROA
@@ -177,60 +171,62 @@ define void @test3() {
; constant folded, and if the i64 doesn't round-trip correctly, you've found
; a bug!
;
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A_SROA_3_0_INSERT_EXT:%.*]] = zext i32 134316040 to i64
+; CHECK-NEXT: [[A_SROA_3_0_INSERT_MASK:%.*]] = and i64 undef, -4294967296
+; CHECK-NEXT: [[A_SROA_3_0_INSERT_INSERT:%.*]] = or i64 [[A_SROA_3_0_INSERT_MASK]], [[A_SROA_3_0_INSERT_EXT]]
+; CHECK-NEXT: [[A_SROA_0_0_INSERT_EXT:%.*]] = zext i32 8 to i64
+; CHECK-NEXT: [[A_SROA_0_0_INSERT_SHIFT:%.*]] = shl i64 [[A_SROA_0_0_INSERT_EXT]], 32
+; CHECK-NEXT: [[A_SROA_0_0_INSERT_MASK:%.*]] = and i64 [[A_SROA_3_0_INSERT_INSERT]], 4294967295
+; CHECK-NEXT: [[A_SROA_0_0_INSERT_INSERT:%.*]] = or i64 [[A_SROA_0_0_INSERT_MASK]], [[A_SROA_0_0_INSERT_SHIFT]]
+; CHECK-NEXT: call void @f(i64 [[A_SROA_0_0_INSERT_INSERT]], i32 8)
+; CHECK-NEXT: ret void
+;
entry:
%a = alloca { i32, i24 }, align 4
-; CHECK-NOT: alloca
store i64 34494054408, ptr %a
%tmp1 = load i64, ptr %a, align 4
%tmp3 = load i32, ptr %a, align 4
-; CHECK: %[[HI_EXT:.*]] = zext i32 134316040 to i64
-; CHECK: %[[HI_INPUT:.*]] = and i64 undef, -4294967296
-; CHECK: %[[HI_MERGE:.*]] = or i64 %[[HI_INPUT]], %[[HI_EXT]]
-; CHECK: %[[LO_EXT:.*]] = zext i32 8 to i64
-; CHECK: %[[LO_SHL:.*]] = shl i64 %[[LO_EXT]], 32
-; CHECK: %[[LO_INPUT:.*]] = and i64 %[[HI_MERGE]], 4294967295
-; CHECK: %[[LO_MERGE:.*]] = or i64 %[[LO_INPUT]], %[[LO_SHL]]
call void @f(i64 %tmp1, i32 %tmp3)
-; CHECK: call void @f(i64 %[[LO_MERGE]], i32 8)
ret void
-; CHECK: ret void
}
define void @test4() {
-; CHECK-LABEL: @test4
-;
; Much like @test3, this is specifically testing big-endian management of data.
; Also similarly, it uses constants with particular bits set to help track
; whether values are corrupted, and can be easily evaluated by running through
; -instcombine to see that the i64 round-trips.
;
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A_SROA_0_0_EXTRACT_SHIFT:%.*]] = lshr i64 34494054408, 32
+; CHECK-NEXT: [[A_SROA_0_0_EXTRACT_TRUNC:%.*]] = trunc i64 [[A_SROA_0_0_EXTRACT_SHIFT]] to i32
+; CHECK-NEXT: [[A_SROA_3_0_EXTRACT_TRUNC:%.*]] = trunc i64 34494054408 to i32
+; CHECK-NEXT: [[A_SROA_3_0_INSERT_EXT:%.*]] = zext i32 [[A_SROA_3_0_EXTRACT_TRUNC]] to i64
+; CHECK-NEXT: [[A_SROA_3_0_INSERT_MASK:%.*]] = and i64 undef, -4294967296
+; CHECK-NEXT: [[A_SROA_3_0_INSERT_INSERT:%.*]] = or i64 [[A_SROA_3_0_INSERT_MASK]], [[A_SROA_3_0_INSERT_EXT]]
+; CHECK-NEXT: [[A_SROA_0_0_INSERT_EXT:%.*]] = zext i32 [[A_SROA_0_0_EXTRACT_TRUNC]] to i64
+; CHECK-NEXT: [[A_SROA_0_0_INSERT_SHIFT:%.*]] = shl i64 [[A_SROA_0_0_INSERT_EXT]], 32
+; CHECK-NEXT: [[A_SROA_0_0_INSERT_MASK:%.*]] = and i64 [[A_SROA_3_0_INSERT_INSERT]], 4294967295
+; CHECK-NEXT: [[A_SROA_0_0_INSERT_INSERT:%.*]] = or i64 [[A_SROA_0_0_INSERT_MASK]], [[A_SROA_0_0_INSERT_SHIFT]]
+; CHECK-NEXT: call void @f(i64 [[A_SROA_0_0_INSERT_INSERT]], i32 [[A_SROA_0_0_EXTRACT_TRUNC]])
+; CHECK-NEXT: ret void
+;
entry:
%a = alloca { i32, i24 }, align 4
%a2 = alloca i64, align 4
-; CHECK-NOT: alloca
store i64 34494054408, ptr %a2
call void @llvm.memcpy.p0.p0.i64(ptr align 4 %a, ptr align 4 %a2, i64 8, i1 false)
-; CHECK: %[[LO_SHR:.*]] = lshr i64 34494054408, 32
-; CHECK: %[[LO_START:.*]] = trunc i64 %[[LO_SHR]] to i32
-; CHECK: %[[HI_START:.*]] = trunc i64 34494054408 to i32
%tmp3 = load i64, ptr %a, align 4
%tmp5 = load i32, ptr %a, align 4
-; CHECK: %[[HI_EXT:.*]] = zext i32 %[[HI_START]] to i64
-; CHECK: %[[HI_INPUT:.*]] = and i64 undef, -4294967296
-; CHECK: %[[HI_MERGE:.*]] = or i64 %[[HI_INPUT]], %[[HI_EXT]]
-; CHECK: %[[LO_EXT:.*]] = zext i32 %[[LO_START]] to i64
-; CHECK: %[[LO_SHL:.*]] = shl i64 %[[LO_EXT]], 32
-; CHECK: %[[LO_INPUT:.*]] = and i64 %[[HI_MERGE]], 4294967295
-; CHECK: %[[LO_MERGE:.*]] = or i64 %[[LO_INPUT]], %[[LO_SHL]]
call void @f(i64 %tmp3, i32 %tmp5)
-; CHECK: call void @f(i64 %[[LO_MERGE]], i32 %[[LO_START]])
ret void
-; CHECK: ret void
}
declare void @llvm.memcpy.p0.p0.i64(ptr, ptr, i64, i1)
diff --git a/llvm/test/Transforms/SROA/dbg-addr-diamond.ll b/llvm/test/Transforms/SROA/dbg-addr-diamond.ll
index 7d75b90d756f..652fc82b0fb2 100644
--- a/llvm/test/Transforms/SROA/dbg-addr-diamond.ll
+++ b/llvm/test/Transforms/SROA/dbg-addr-diamond.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -use-dbg-addr -passes=sroa -S < %s | FileCheck %s
; ModuleID = '<stdin>'
@@ -11,6 +12,29 @@ target triple = "x86_64-pc-windows-msvc19.0.24215"
; Function Attrs: nounwind uwtable
define void @if_else(i32 %cond, i32 %a, i32 %b) !dbg !8 {
+; CHECK-LABEL: @if_else(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: call void @llvm.dbg.value(metadata i32 [[A:%.*]], metadata [[META20:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 32)), !dbg [[DBG21:![0-9]+]]
+; CHECK-NEXT: call void @llvm.dbg.value(metadata i32 [[B:%.*]], metadata [[META20]], metadata !DIExpression(DW_OP_LLVM_fragment, 32, 32)), !dbg [[DBG21]]
+; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[COND:%.*]], 0, !dbg [[DBG22:![0-9]+]]
+; CHECK-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]], !dbg [[DBG24:![0-9]+]]
+; CHECK: if.then:
+; CHECK-NEXT: call void @llvm.dbg.value(metadata i32 0, metadata [[META20]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 32)), !dbg [[DBG21]]
+; CHECK-NEXT: call void @llvm.dbg.value(metadata i32 [[A]], metadata [[META20]], metadata !DIExpression(DW_OP_LLVM_fragment, 32, 32)), !dbg [[DBG21]]
+; CHECK-NEXT: br label [[IF_END:%.*]], !dbg [[DBG25:![0-9]+]]
+; CHECK: if.else:
+; CHECK-NEXT: call void @llvm.dbg.value(metadata i32 [[B]], metadata [[META20]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 32)), !dbg [[DBG21]]
+; CHECK-NEXT: call void @llvm.dbg.value(metadata i32 0, metadata [[META20]], metadata !DIExpression(DW_OP_LLVM_fragment, 32, 32)), !dbg [[DBG21]]
+; CHECK-NEXT: br label [[IF_END]]
+; CHECK: if.end:
+; CHECK-NEXT: [[P_SROA_4_0:%.*]] = phi i32 [ [[A]], [[IF_THEN]] ], [ 0, [[IF_ELSE]] ], !dbg [[DBG27:![0-9]+]]
+; CHECK-NEXT: [[P_SROA_0_0:%.*]] = phi i32 [ 0, [[IF_THEN]] ], [ [[B]], [[IF_ELSE]] ], !dbg [[DBG27]]
+; CHECK-NEXT: call void @llvm.dbg.value(metadata i32 [[P_SROA_0_0]], metadata [[META20]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 32)), !dbg [[DBG21]]
+; CHECK-NEXT: call void @llvm.dbg.value(metadata i32 [[P_SROA_4_0]], metadata [[META20]], metadata !DIExpression(DW_OP_LLVM_fragment, 32, 32)), !dbg [[DBG21]]
+; CHECK-NEXT: store i32 [[P_SROA_0_0]], ptr @pair, align 4, !dbg [[DBG28:![0-9]+]]
+; CHECK-NEXT: store i32 [[P_SROA_4_0]], ptr getelementptr inbounds (i8, ptr @pair, i64 4), align 4, !dbg [[DBG28]]
+; CHECK-NEXT: ret void
+;
entry:
%p = alloca %struct.Pair, align 4
call void @llvm.dbg.addr(metadata ptr %p, metadata !20, metadata !DIExpression()), !dbg !26
@@ -37,23 +61,7 @@ if.end: ; preds = %if.else, %if.then
ret void
}
-; CHECK-LABEL: define void @if_else(i32 %cond, i32 %a, i32 %b)
-; CHECK: entry:
-; CHECK: call void @llvm.dbg.value(metadata i32 %a, metadata ![[PVAR:[0-9]+]], metadata ![[XFRAG:DIExpression\(DW_OP_LLVM_fragment, 0, 32\)]])
-; CHECK: call void @llvm.dbg.value(metadata i32 %b, metadata ![[PVAR]], metadata ![[YFRAG:DIExpression\(DW_OP_LLVM_fragment, 32, 32\)]])
-; CHECK: if.then:
-; CHECK: call void @llvm.dbg.value(metadata i32 0, metadata ![[PVAR]], metadata ![[XFRAG]])
-; CHECK: call void @llvm.dbg.value(metadata i32 %a, metadata ![[PVAR]], metadata ![[YFRAG]])
-; CHECK: if.else:
-; CHECK: call void @llvm.dbg.value(metadata i32 %b, metadata ![[PVAR]], metadata ![[XFRAG]])
-; CHECK: call void @llvm.dbg.value(metadata i32 0, metadata ![[PVAR]], metadata ![[YFRAG]])
-; CHECK: if.end:
-; CHECK: %p.sroa.4.0 = phi i32 [ %a, %if.then ], [ 0, %if.else ]
-; CHECK: %p.sroa.0.0 = phi i32 [ 0, %if.then ], [ %b, %if.else ]
-; CHECK: call void @llvm.dbg.value(metadata i32 %p.sroa.0.0, metadata ![[PVAR]], metadata ![[XFRAG]])
-; CHECK: call void @llvm.dbg.value(metadata i32 %p.sroa.4.0, metadata ![[PVAR]], metadata ![[YFRAG]])
-; CHECK: ![[PVAR]] = !DILocalVariable(name: "p", {{.*}})
; Function Attrs: argmemonly nounwind
declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i1) #2
diff --git a/llvm/test/Transforms/SROA/dbg-inline.ll b/llvm/test/Transforms/SROA/dbg-inline.ll
index 883fe28cf893..48498e98c462 100644
--- a/llvm/test/Transforms/SROA/dbg-inline.ll
+++ b/llvm/test/Transforms/SROA/dbg-inline.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; Test that SROA can deal with allocas that have more than one
; dbg.declare hanging off of it.
@@ -10,15 +11,19 @@ target triple = "x86_64-apple-macosx10.15.0"
; Function Attrs: noinline optnone ssp uwtable
define i64 @_Z1g4pair(i64 %p.coerce0, i64 %p.coerce1) #0 !dbg !8 {
+; CHECK-LABEL: @_Z1g4pair(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: call void @llvm.dbg.value(metadata i64 [[P_COERCE0:%.*]], metadata [[META16:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64)), !dbg [[DBG17:![0-9]+]]
+; CHECK-NEXT: call void @llvm.dbg.value(metadata i64 [[P_COERCE0]], metadata [[META18:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64)), !dbg [[DBG20:![0-9]+]]
+; CHECK-NEXT: call void @llvm.dbg.value(metadata i64 [[P_COERCE1:%.*]], metadata [[META16]], metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64)), !dbg [[DBG17]]
+; CHECK-NEXT: call void @llvm.dbg.value(metadata i64 [[P_COERCE1]], metadata [[META18]], metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64)), !dbg [[DBG20]]
+; CHECK-NEXT: ret i64 [[P_COERCE0]], !dbg [[DBG22:![0-9]+]]
+;
entry:
%p = alloca %struct.pair, align 8
store i64 %p.coerce0, ptr %p, align 8
%0 = getelementptr inbounds %struct.pair, ptr %p, i32 0, i32 1
store i64 %p.coerce1, ptr %0, align 8
- ; CHECK-DAG: call void @llvm.dbg.value(metadata i64 %p.coerce0, metadata ![[VAR:[0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64)), !dbg ![[LOC:[0-9]+]]
- ; CHECK-DAG: call void @llvm.dbg.value(metadata i64 %p.coerce1, metadata ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64)), !dbg ![[LOC]]
- ; CHECK-DAG: call void @llvm.dbg.value(metadata i64 %p.coerce0, metadata ![[INLINED_VAR:[0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64)), !dbg ![[INLINED_LOC:[0-9]+]]
- ; CHECK-DAG: call void @llvm.dbg.value(metadata i64 %p.coerce1, metadata ![[INLINED_VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64)), !dbg ![[INLINED_LOC]]
call void @llvm.dbg.declare(metadata ptr %p, metadata !17, metadata !DIExpression()), !dbg !18
call void @llvm.dbg.declare(metadata ptr %p, metadata !21, metadata !DIExpression()), !dbg !23
%x2 = load i64, ptr %p, align 8, !dbg !25
@@ -55,15 +60,11 @@ attributes #2 = { argmemonly nounwind willreturn }
!15 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !13, file: !9, line: 1, baseType: !12, size: 64)
!16 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !13, file: !9, line: 1, baseType: !12, size: 64, offset: 64)
!17 = !DILocalVariable(name: "p", arg: 1, scope: !8, file: !9, line: 9, type: !13)
-; CHECK: ![[LOC]] = !DILocation
-; CHECK-NOT: inlinedAt
-; CHECK: =
!18 = !DILocation(line: 9, column: 27, scope: !8)
!19 = !DILocation(line: 10, column: 12, scope: !8)
!20 = !DILocation(line: 10, column: 10, scope: !8)
!21 = !DILocalVariable(name: "p", arg: 1, scope: !22, file: !9, line: 5, type: !13)
!22 = distinct !DISubprogram(name: "f", linkageName: "_ZL1f4pair", scope: !9, file: !9, line: 5, type: !10, scopeLine: 5, flags: DIFlagPrototyped, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition, unit: !0, retainedNodes: !2)
-; CHECK: ![[INLINED_LOC]] = !DILocation({{.*}}inlinedAt
!23 = !DILocation(line: 5, column: 27, scope: !22, inlinedAt: !24)
!24 = distinct !DILocation(line: 10, column: 10, scope: !8)
!25 = !DILocation(line: 6, column: 12, scope: !22, inlinedAt: !24)
diff --git a/llvm/test/Transforms/SROA/dead-inst.ll b/llvm/test/Transforms/SROA/dead-inst.ll
index a685123fa34c..299bed8b0e5f 100644
--- a/llvm/test/Transforms/SROA/dead-inst.ll
+++ b/llvm/test/Transforms/SROA/dead-inst.ll
@@ -3,12 +3,6 @@
; dead instructions. Ensure that this invalidates analyses required
; for other passes.
; RUN: opt < %s -passes=bdce,sroa,bdce -o %t -debug-pass-manager 2>&1 | FileCheck %s
-; CHECK: Running pass: BDCEPass on H
-; CHECK: Running analysis: DemandedBitsAnalysis on H
-; CHECK: Running pass: SROAPass on H
-; CHECK: Invalidating analysis: DemandedBitsAnalysis on H
-; CHECK: Running pass: BDCEPass on H
-; CHECK: Running analysis: DemandedBitsAnalysis on H
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-grtev4-linux-gnu"
@@ -91,3 +85,5 @@ declare void @llvm.lifetime.start.p0(i64, ptr nocapture)
; Function Attrs: argmemonly nounwind
declare void @llvm.lifetime.end.p0(i64, ptr nocapture)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/Transforms/SROA/fca.ll b/llvm/test/Transforms/SROA/fca.ll
index 3ffeadd8bf89..57aa1b079eae 100644
--- a/llvm/test/Transforms/SROA/fca.ll
+++ b/llvm/test/Transforms/SROA/fca.ll
@@ -1,13 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=sroa -S | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
define { i32, i32 } @test0(i32 %x, i32 %y, { i32, i32 } %v) {
; CHECK-LABEL: @test0(
-; CHECK-NOT: alloca
-; CHECK: insertvalue { i32, i32 }
-; CHECK: insertvalue { i32, i32 }
-; CHECK: ret { i32, i32 }
-
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[V_FCA_0_EXTRACT:%.*]] = extractvalue { i32, i32 } [[V:%.*]], 0
+; CHECK-NEXT: [[V_FCA_1_EXTRACT:%.*]] = extractvalue { i32, i32 } [[V]], 1
+; CHECK-NEXT: [[RESULT_FCA_0_INSERT:%.*]] = insertvalue { i32, i32 } poison, i32 [[X:%.*]], 0
+; CHECK-NEXT: [[RESULT_FCA_1_INSERT:%.*]] = insertvalue { i32, i32 } [[RESULT_FCA_0_INSERT]], i32 [[Y:%.*]], 1
+; CHECK-NEXT: ret { i32, i32 } [[RESULT_FCA_1_INSERT]]
+;
entry:
%a = alloca { i32, i32 }
@@ -27,12 +30,16 @@ define { i32, i32 } @test1(i32 %x, i32 %y) {
; split the volatile load and store here but must produce volatile scalar loads
; and stores from them.
; CHECK-LABEL: @test1(
-; CHECK: alloca
-; CHECK: alloca
-; CHECK: load volatile { i32, i32 }, ptr
-; CHECK: store volatile { i32, i32 }
-; CHECK: ret { i32, i32 }
-
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A:%.*]] = alloca { i32, i32 }, align 8
+; CHECK-NEXT: [[B:%.*]] = alloca { i32, i32 }, align 8
+; CHECK-NEXT: store i32 [[X:%.*]], ptr [[A]], align 8
+; CHECK-NEXT: [[A_4_GEP2_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 4
+; CHECK-NEXT: store i32 [[Y:%.*]], ptr [[A_4_GEP2_SROA_IDX]], align 4
+; CHECK-NEXT: [[A_0_RESULT:%.*]] = load volatile { i32, i32 }, ptr [[A]], align 8
+; CHECK-NEXT: store volatile { i32, i32 } [[A_0_RESULT]], ptr [[B]], align 8
+; CHECK-NEXT: ret { i32, i32 } [[A_0_RESULT]]
+;
entry:
%a = alloca { i32, i32 }
%b = alloca { i32, i32 }
diff --git a/llvm/test/Transforms/SROA/mem-par-metadata-sroa-cast.ll b/llvm/test/Transforms/SROA/mem-par-metadata-sroa-cast.ll
index 9adb896a165c..032dd1701e59 100644
--- a/llvm/test/Transforms/SROA/mem-par-metadata-sroa-cast.ll
+++ b/llvm/test/Transforms/SROA/mem-par-metadata-sroa-cast.ll
@@ -1,18 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=sroa -S | FileCheck %s
;
; Make sure the llvm.access.group meta-data is preserved
; when a load/store is replaced with another load/store by sroa
; Ensure this is done for casting too.
;
-; CHECK: entry:
-; CHECK: load i32, ptr {{.*}}, !llvm.access.group [[DISTINCT:![0-9]*]]
-; CHECK: load i32, ptr {{.*}}, !llvm.access.group [[DISTINCT]]
-; CHECK: ret void
-; CHECK: [[DISTINCT]] = distinct !{}
%CMPLX = type { float, float }
define dso_local void @test() {
+; CHECK-LABEL: @test(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[PART:%.*]] = alloca [[CMPLX:%.*]], align 8
+; CHECK-NEXT: [[DUMMY:%.*]] = sext i16 0 to i64
+; CHECK-NEXT: [[T:%.*]] = getelementptr [[CMPLX]], ptr [[PART]], i64 [[DUMMY]]
+; CHECK-NEXT: [[X371:%.*]] = load i32, ptr [[T]], align 8, !llvm.access.group [[ACC_GRP0:![0-9]+]]
+; CHECK-NEXT: [[T_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[T]], i64 4
+; CHECK-NEXT: [[X372:%.*]] = load i32, ptr [[T_SROA_IDX]], align 4, !llvm.access.group [[ACC_GRP0]]
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[X371]] to float
+; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[X372]] to float
+; CHECK-NEXT: ret void
+;
entry:
%PART = alloca %CMPLX, align 8
%PREV = alloca %CMPLX, align 8
diff --git a/llvm/test/Transforms/SROA/mem-par-metadata-sroa.ll b/llvm/test/Transforms/SROA/mem-par-metadata-sroa.ll
index 57d36739a609..04d5e6ac46cb 100644
--- a/llvm/test/Transforms/SROA/mem-par-metadata-sroa.ll
+++ b/llvm/test/Transforms/SROA/mem-par-metadata-sroa.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=sroa -S | FileCheck %s
;
; Make sure the llvm.access.group meta-data is preserved
@@ -12,16 +13,16 @@
; Complex() : real_(0), imaginary_(0) { }
; Complex(float real, float imaginary) : real_(real), imaginary_(imaginary) { }
; Complex(const Complex &rhs) : real_(rhs.real()), imaginary_(rhs.imaginary()) { }
-;
+;
; inline float real() const { return real_; }
; inline float imaginary() const { return imaginary_; }
-;
+;
; Complex operator+(const Complex& rhs) const
; {
; return Complex(real_ + rhs.real_, imaginary_ + rhs.imaginary_);
; }
; };
-;
+;
; void test(Complex *out, long size)
; {
; #pragma clang loop vectorize(assume_safety)
@@ -31,13 +32,6 @@
; }
; }
-; CHECK: for.body:
-; CHECK-NOT: store i32 %{{.*}}, ptr %{{.*}}, align 4
-; CHECK: store i32 %{{.*}}, ptr %{{.*}}, align 4, !llvm.access.group !1
-; CHECK-NOT: store i32 %{{.*}}, ptr %{{.*}}, align 4
-; CHECK: store i32 %{{.*}}, ptr %{{.*}}, align 4, !llvm.access.group !1
-; CHECK-NOT: store i32 %{{.*}}, ptr %{{.*}}, align 4
-; CHECK: br label
; ModuleID = '<stdin>'
source_filename = "mem-par-metadata-sroa1.cpp"
@@ -48,6 +42,31 @@ target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: norecurse nounwind uwtable
define void @_Z4testP7Complexl(ptr nocapture %out, i64 %size) local_unnamed_addr #0 {
+; CHECK-LABEL: @_Z4testP7Complexl(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_COND:%.*]]
+; CHECK: for.cond:
+; CHECK-NEXT: [[OFFSET_0:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY:%.*]] ]
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[OFFSET_0]], [[SIZE:%.*]]
+; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[CLASS_COMPLEX:%.*]], ptr [[OUT:%.*]], i64 [[OFFSET_0]]
+; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP1:![0-9]+]]
+; CHECK-NEXT: [[IMAGINARY__I_I:%.*]] = getelementptr inbounds [[CLASS_COMPLEX]], ptr [[ARRAYIDX]], i64 0, i32 1
+; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[IMAGINARY__I_I]], align 4, !llvm.access.group [[ACC_GRP1]]
+; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [[CLASS_COMPLEX]], ptr [[OUT]], i64 [[OFFSET_0]]
+; CHECK-NEXT: [[ADD_I:%.*]] = fadd float [[TMP0]], [[TMP0]]
+; CHECK-NEXT: [[ADD4_I:%.*]] = fadd float [[TMP1]], [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[ADD_I]] to i32
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[ADD4_I]] to i32
+; CHECK-NEXT: store i32 [[TMP2]], ptr [[ARRAYIDX1]], align 4, !llvm.access.group [[ACC_GRP1]]
+; CHECK-NEXT: [[ARRAYIDX1_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[ARRAYIDX1]], i64 4
+; CHECK-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX1_SROA_IDX]], align 4, !llvm.access.group [[ACC_GRP1]]
+; CHECK-NEXT: [[INC]] = add nsw i64 [[OFFSET_0]], 1
+; CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
%t0 = alloca %class.Complex, align 4
%ref.tmp = alloca i64, align 8
diff --git a/llvm/test/Transforms/SROA/non-capturing-call-readonly.ll b/llvm/test/Transforms/SROA/non-capturing-call-readonly.ll
index 229c4730e26c..33e6003c1560 100644
--- a/llvm/test/Transforms/SROA/non-capturing-call-readonly.ll
+++ b/llvm/test/Transforms/SROA/non-capturing-call-readonly.ll
@@ -21,6 +21,7 @@ define i32 @alloca_used_in_call(ptr %data, i64 %n) {
; CHECK-NEXT: [[I0:%.*]] = call i32 @user_of_alloca(ptr [[RETVAL]])
; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[RETVAL]], align 4
; CHECK-NEXT: ret i32 [[I1]]
+;
entry:
%retval = alloca i32, align 4
store i32 0, ptr %retval, align 4
@@ -63,6 +64,7 @@ define i32 @alloca_captured_in_call(ptr %data, i64 %n) {
; CHECK-NEXT: [[I0:%.*]] = call i32 @capture_of_alloca(ptr [[RETVAL]])
; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[RETVAL]], align 4
; CHECK-NEXT: ret i32 [[I1]]
+;
entry:
%retval = alloca i32, align 4
store i32 0, ptr %retval, align 4
@@ -105,6 +107,7 @@ define i32 @alloca_not_captured_as_per_operand_attr(ptr %data, i64 %n) {
; CHECK-NEXT: [[I0:%.*]] = call i32 @capture_of_alloca(ptr nocapture [[RETVAL]])
; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[RETVAL]], align 4
; CHECK-NEXT: ret i32 [[I1]]
+;
entry:
%retval = alloca i32, align 4
store i32 0, ptr %retval, align 4
@@ -147,6 +150,7 @@ define i32 @alloca_not_captured_and_readonly_as_per_operand_attr(ptr %data, i64
; CHECK-NEXT: [[I0:%.*]] = call i32 @capture_of_alloca(ptr nocapture readonly [[RETVAL]])
; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[RETVAL]], align 4
; CHECK-NEXT: ret i32 [[I1]]
+;
entry:
%retval = alloca i32, align 4
store i32 0, ptr %retval, align 4
@@ -189,6 +193,7 @@ define i32 @alloca_not_captured_as_per_operand_attr_and_readonly_as_per_callbase
; CHECK-NEXT: [[I0:%.*]] = call i32 @capture_of_alloca(ptr nocapture [[RETVAL]]) #[[ATTR2:[0-9]+]]
; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[RETVAL]], align 4
; CHECK-NEXT: ret i32 [[I1]]
+;
entry:
%retval = alloca i32, align 4
store i32 0, ptr %retval, align 4
@@ -231,6 +236,7 @@ define i32 @alloca_not_readonly_as_per_operand_attr(ptr %data, i64 %n) {
; CHECK-NEXT: [[I0:%.*]] = call i32 @capture_of_alloca(ptr readonly [[RETVAL]])
; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[RETVAL]], align 4
; CHECK-NEXT: ret i32 [[I1]]
+;
entry:
%retval = alloca i32, align 4
store i32 0, ptr %retval, align 4
@@ -273,6 +279,7 @@ define i32 @alloca_with_gep_used_in_call(ptr %data, i64 %n) {
; CHECK-NEXT: [[I0:%.*]] = call i32 @user_of_alloca(ptr [[RETVAL]])
; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[RETVAL]], align 4
; CHECK-NEXT: ret i32 [[I1]]
+;
entry:
%retval = alloca i32, align 4
store i32 0, ptr %retval, align 4
@@ -315,6 +322,7 @@ define i32 @alloca_captured_second_arg(ptr %data, i64 %n) {
; CHECK-NEXT: [[I0:%.*]] = call i32 @capture_with_multiple_args(ptr [[RETVAL]], ptr [[RETVAL]])
; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[RETVAL]], align 4
; CHECK-NEXT: ret i32 [[I1]]
+;
entry:
%retval = alloca i32, align 4
store i32 0, ptr %retval, align 4
@@ -365,6 +373,7 @@ define i32 @alloca_used_in_maybe_throwing_call(ptr %data, i64 %n) personality pt
; CHECK: end:
; CHECK-NEXT: [[I2:%.*]] = load i32, ptr [[RETVAL]], align 4
; CHECK-NEXT: ret i32 [[I2]]
+;
entry:
%retval = alloca i32, align 4
store i32 0, ptr %retval, align 4
@@ -422,6 +431,7 @@ define i32 @alloca_used_in_maybe_throwing_call_with_same_dests(ptr %data, i64 %n
; CHECK: end:
; CHECK-NEXT: [[I2:%.*]] = load i32, ptr [[RETVAL]], align 4
; CHECK-NEXT: ret i32 [[I2]]
+;
entry:
%retval = alloca i32, align 4
store i32 0, ptr %retval, align 4
@@ -479,6 +489,7 @@ define [2 x i32] @part_of_alloca_used_in_call(ptr %data, i64 %n) {
; CHECK-NEXT: [[I1_FCA_1_LOAD:%.*]] = load i32, ptr [[I1_FCA_1_GEP]], align 4
; CHECK-NEXT: [[I1_FCA_1_INSERT:%.*]] = insertvalue [2 x i32] [[I1_FCA_0_INSERT]], i32 [[I1_FCA_1_LOAD]], 1
; CHECK-NEXT: ret [2 x i32] [[I1_FCA_1_INSERT]]
+;
entry:
%retval.full = alloca [2 x i32], align 4
store [2 x i32] zeroinitializer, ptr %retval.full, align 4
@@ -531,6 +542,7 @@ define [2 x i32] @all_parts_of_alloca_used_in_call_with_multiple_args(ptr %data,
; CHECK-NEXT: [[I1_FCA_1_LOAD:%.*]] = load i32, ptr [[I1_FCA_1_GEP]], align 4
; CHECK-NEXT: [[I1_FCA_1_INSERT:%.*]] = insertvalue [2 x i32] [[I1_FCA_0_INSERT]], i32 [[I1_FCA_1_LOAD]], 1
; CHECK-NEXT: ret [2 x i32] [[I1_FCA_1_INSERT]]
+;
entry:
%retval.full = alloca [2 x i32], align 4
store [2 x i32] zeroinitializer, ptr %retval.full, align 4
@@ -584,6 +596,7 @@ define [2 x i32] @all_parts_of_alloca_used_in_call_with_multiple_args_with_memcp
; CHECK-NEXT: [[I1_FCA_1_LOAD:%.*]] = load i32, ptr [[I1_FCA_1_GEP]], align 4
; CHECK-NEXT: [[I1_FCA_1_INSERT:%.*]] = insertvalue [2 x i32] [[I1_FCA_0_INSERT]], i32 [[I1_FCA_1_LOAD]], 1
; CHECK-NEXT: ret [2 x i32] [[I1_FCA_1_INSERT]]
+;
entry:
%retval.full = alloca [2 x i32], align 4
store [2 x i32] zeroinitializer, ptr %retval.full, align 4
@@ -638,6 +651,7 @@ define [2 x i32] @all_parts_of_alloca_used_in_call_with_multiple_args_with_memcp
; CHECK-NEXT: [[I1_FCA_1_LOAD:%.*]] = load i32, ptr [[I1_FCA_1_GEP]], align 4
; CHECK-NEXT: [[I1_FCA_1_INSERT:%.*]] = insertvalue [2 x i32] [[I1_FCA_0_INSERT]], i32 [[I1_FCA_1_LOAD]], 1
; CHECK-NEXT: ret [2 x i32] [[I1_FCA_1_INSERT]]
+;
entry:
%retval.full = alloca [2 x i32], align 4
store [2 x i32] zeroinitializer, ptr %retval.full, align 4
@@ -691,6 +705,7 @@ define [2 x i32] @part_of_alloca_used_in_call_with_multiple_args(ptr %data, i64
; CHECK-NEXT: [[I1_FCA_1_LOAD:%.*]] = load i32, ptr [[I1_FCA_1_GEP]], align 4
; CHECK-NEXT: [[I1_FCA_1_INSERT:%.*]] = insertvalue [2 x i32] [[I1_FCA_0_INSERT]], i32 [[I1_FCA_1_LOAD]], 1
; CHECK-NEXT: ret [2 x i32] [[I1_FCA_1_INSERT]]
+;
entry:
%retval.full = alloca [2 x i32], align 4
store [2 x i32] zeroinitializer, ptr %retval.full, align 4
@@ -746,6 +761,7 @@ define [2 x i32] @all_parts_of_alloca_used_in_calls_with_multiple_args(ptr %data
; CHECK-NEXT: [[I3_FCA_1_LOAD:%.*]] = load i32, ptr [[I3_FCA_1_GEP]], align 4
; CHECK-NEXT: [[I3_FCA_1_INSERT:%.*]] = insertvalue [2 x i32] [[I3_FCA_0_INSERT]], i32 [[I3_FCA_1_LOAD]], 1
; CHECK-NEXT: ret [2 x i32] [[I3_FCA_1_INSERT]]
+;
entry:
%retval.full = alloca [2 x i32], align 4
%some.another.alloca.full = alloca [42 x i32], align 4
@@ -779,6 +795,7 @@ define i32 @all_uses_of_alloca_are_calls(ptr %data, i64 %n) {
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @user_of_alloca(ptr [[RETVAL]])
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @user_of_alloca(ptr [[RETVAL]])
; CHECK-NEXT: ret i32 0
+;
entry:
%retval = alloca i32, align 4
call i32 @user_of_alloca(ptr %retval)
@@ -800,6 +817,7 @@ define i64 @do_schedule_instrs_for_dce_after_fixups() {
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @user_of_alloca(ptr [[ADD_PTR]])
; CHECK-NEXT: [[LD:%.*]] = load i64, ptr [[C]], align 4
; CHECK-NEXT: ret i64 [[LD]]
+;
entry:
%c = alloca i64, align 2
call void @llvm.lifetime.start.p0(i64 1, ptr %c)
@@ -820,6 +838,7 @@ define void @dont_transform_store_only() {
; CHECK-NEXT: store i8 0, ptr [[A]], align 1
; CHECK-NEXT: call void @byte_user_of_alloca(ptr [[A]])
; CHECK-NEXT: ret void
+;
entry:
%a = alloca i8
store i8 0, ptr %a
@@ -833,6 +852,7 @@ define i8 @dont_transform_load_only() {
; CHECK-NEXT: call void @byte_user_of_alloca(ptr [[A]])
; CHECK-NEXT: [[R:%.*]] = load i8, ptr [[A]], align 1
; CHECK-NEXT: ret i8 [[R]]
+;
entry:
%a = alloca i8
call void @byte_user_of_alloca(ptr %a)
@@ -847,6 +867,7 @@ define i8 @transform_load_and_store() {
; CHECK-NEXT: call void @byte_user_of_alloca(ptr [[A]])
; CHECK-NEXT: [[R:%.*]] = load i8, ptr [[A]], align 1
; CHECK-NEXT: ret i8 [[R]]
+;
entry:
%a = alloca i8
store i8 0, ptr %a
@@ -874,6 +895,7 @@ define [2 x i32] @select_of_ptrs(ptr %data, i1 %c, i32 %v) {
; CHECK-NEXT: [[I1_FCA_1_LOAD:%.*]] = load i32, ptr [[I1_FCA_1_GEP]], align 4
; CHECK-NEXT: [[I1_FCA_1_INSERT:%.*]] = insertvalue [2 x i32] [[I1_FCA_0_INSERT]], i32 [[I1_FCA_1_LOAD]], 1
; CHECK-NEXT: ret [2 x i32] [[I1_FCA_1_INSERT]]
+;
entry:
%retval.full = alloca [2 x i32], align 4
store [2 x i32] zeroinitializer, ptr %retval.full, align 4
diff --git a/llvm/test/Transforms/SROA/non-integral-pointers.ll b/llvm/test/Transforms/SROA/non-integral-pointers.ll
index 10d5270a1ea2..99be316c4732 100644
--- a/llvm/test/Transforms/SROA/non-integral-pointers.ll
+++ b/llvm/test/Transforms/SROA/non-integral-pointers.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes=sroa -S < %s | FileCheck %s
; This test checks that SROA does not introduce ptrtoint and inttoptr
@@ -10,8 +11,17 @@ target triple = "x86_64-unknown-linux-gnu"
define void @f0(i1 %alwaysFalse, i64 %val) {
; CHECK-LABEL: @f0(
-; CHECK-NOT: inttoptr
-; CHECK-NOT: ptrtoint
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[LOC:%.*]] = alloca i64, align 8
+; CHECK-NEXT: store i64 [[VAL:%.*]], ptr [[LOC]], align 8
+; CHECK-NEXT: br i1 [[ALWAYSFALSE:%.*]], label [[NEVERTAKEN:%.*]], label [[ALWAYSTAKEN:%.*]]
+; CHECK: neverTaken:
+; CHECK-NEXT: [[LOC_0_PTR:%.*]] = load ptr addrspace(4), ptr [[LOC]], align 8
+; CHECK-NEXT: store i8 5, ptr addrspace(4) [[LOC_0_PTR]], align 1
+; CHECK-NEXT: ret void
+; CHECK: alwaysTaken:
+; CHECK-NEXT: ret void
+;
entry:
%loc = alloca i64
store i64 %val, ptr %loc
@@ -28,8 +38,16 @@ alwaysTaken:
define i64 @f1(i1 %alwaysFalse, ptr addrspace(4) %val) {
; CHECK-LABEL: @f1(
-; CHECK-NOT: inttoptr
-; CHECK-NOT: ptrtoint
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[LOC:%.*]] = alloca ptr addrspace(4), align 8
+; CHECK-NEXT: store ptr addrspace(4) [[VAL:%.*]], ptr [[LOC]], align 8
+; CHECK-NEXT: br i1 [[ALWAYSFALSE:%.*]], label [[NEVERTAKEN:%.*]], label [[ALWAYSTAKEN:%.*]]
+; CHECK: neverTaken:
+; CHECK-NEXT: [[LOC_0_INT:%.*]] = load i64, ptr [[LOC]], align 8
+; CHECK-NEXT: ret i64 [[LOC_0_INT]]
+; CHECK: alwaysTaken:
+; CHECK-NEXT: ret i64 42
+;
entry:
%loc = alloca ptr addrspace(4)
store ptr addrspace(4) %val, ptr %loc
@@ -45,8 +63,16 @@ alwaysTaken:
define ptr addrspace(4) @memset(i1 %alwaysFalse) {
; CHECK-LABEL: @memset(
-; CHECK-NOT: inttoptr
-; CHECK-NOT: ptrtoint
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[X:%.*]] = alloca ptr addrspace(4), align 8
+; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[X]], i8 5, i64 8, i1 false)
+; CHECK-NEXT: br i1 [[ALWAYSFALSE:%.*]], label [[NEVERTAKEN:%.*]], label [[ALWAYSTAKEN:%.*]]
+; CHECK: neverTaken:
+; CHECK-NEXT: [[X_0_X_FIELD_LD_0:%.*]] = load ptr addrspace(4), ptr [[X]], align 8
+; CHECK-NEXT: ret ptr addrspace(4) [[X_0_X_FIELD_LD_0]]
+; CHECK: alwaysTaken:
+; CHECK-NEXT: ret ptr addrspace(4) null
+;
entry:
%x = alloca ptr addrspace(4)
call void @llvm.memset.p0.i64(ptr align 8 %x, i8 5, i64 16, i1 false)
@@ -55,7 +81,7 @@ entry:
neverTaken:
%x.field.ld.0 = load ptr addrspace(4), ptr %x
ret ptr addrspace(4) %x.field.ld.0
-
+
alwaysTaken:
ret ptr addrspace(4) null
}
@@ -66,8 +92,16 @@ alwaysTaken:
;; usually be gotten by instcombine.
define ptr addrspace(4) @memset_null(i1 %alwaysFalse) {
; CHECK-LABEL: @memset_null(
-; CHECK-NOT: inttoptr
-; CHECK-NOT: ptrtoint
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[X:%.*]] = alloca ptr addrspace(4), align 8
+; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[X]], i8 0, i64 8, i1 false)
+; CHECK-NEXT: br i1 [[ALWAYSFALSE:%.*]], label [[NEVERTAKEN:%.*]], label [[ALWAYSTAKEN:%.*]]
+; CHECK: neverTaken:
+; CHECK-NEXT: [[X_0_X_FIELD_LD_0:%.*]] = load ptr addrspace(4), ptr [[X]], align 8
+; CHECK-NEXT: ret ptr addrspace(4) [[X_0_X_FIELD_LD_0]]
+; CHECK: alwaysTaken:
+; CHECK-NEXT: ret ptr addrspace(4) null
+;
entry:
%x = alloca ptr addrspace(4)
call void @llvm.memset.p0.i64(ptr align 8 %x, i8 0, i64 16, i1 false)
@@ -76,17 +110,20 @@ entry:
neverTaken:
%x.field.ld.0 = load ptr addrspace(4), ptr %x
ret ptr addrspace(4) %x.field.ld.0
-
+
alwaysTaken:
ret ptr addrspace(4) null
}
%union.anon = type { ptr }
-; CHECK-LABEL: @f2(
-; CHECK-NOT: ptr2int
-; CHECK-NOT: int2ptr
define ptr at f2(ptr addrspace(4) %p) {
+; CHECK-LABEL: @f2(
+; CHECK-NEXT: [[DOTSROA_0:%.*]] = alloca ptr, align 8
+; CHECK-NEXT: store ptr addrspace(4) [[P:%.*]], ptr [[DOTSROA_0]], align 8
+; CHECK-NEXT: [[DOTSROA_0_0__SROA_0_0_:%.*]] = load ptr, ptr [[DOTSROA_0]], align 8
+; CHECK-NEXT: ret ptr [[DOTSROA_0_0__SROA_0_0_]]
+;
%1 = alloca %union.anon, align 8
store ptr addrspace(4) %p, ptr %1, align 8
%2 = load ptr, ptr %1, align 8
diff --git a/llvm/test/Transforms/SROA/phi-and-select.ll b/llvm/test/Transforms/SROA/phi-and-select.ll
index 255fe341f324..15b71590881c 100644
--- a/llvm/test/Transforms/SROA/phi-and-select.ll
+++ b/llvm/test/Transforms/SROA/phi-and-select.ll
@@ -270,7 +270,6 @@ define i32 @test7(i1 %c1) {
; CHECK-NEXT: [[P_SROA_SPECULATED:%.*]] = phi i32 [ 0, [[GOOD]] ], [ [[P_SROA_SPECULATE_LOAD_BAD]], [[BAD]] ]
; CHECK-NEXT: ret i32 [[P_SROA_SPECULATED]]
;
-
entry:
%X = alloca i32
br i1 %c1, label %good, label %bad
@@ -293,6 +292,7 @@ exit:
define i32 @test8(i32 %b, ptr %ptr) {
; Ensure that we rewrite allocas to the used type when that use is hidden by
; a PHI that can be speculated.
+;
; CHECK-LABEL: @test8(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TEST:%.*]] = icmp ne i32 [[B:%.*]], 0
@@ -306,7 +306,6 @@ define i32 @test8(i32 %b, ptr %ptr) {
; CHECK-NEXT: [[PHI_SROA_SPECULATED:%.*]] = phi i32 [ undef, [[ELSE]] ], [ [[PHI_SROA_SPECULATE_LOAD_THEN]], [[THEN]] ]
; CHECK-NEXT: ret i32 [[PHI_SROA_SPECULATED]]
;
-
entry:
%f = alloca float
%test = icmp ne i32 %b, 0
@@ -326,6 +325,7 @@ exit:
define i32 @test9(i32 %b, ptr %ptr) {
; Same as @test8 but for a select rather than a PHI node.
+;
; CHECK-LABEL: @test9(
; CHECK-NEXT: entry:
; CHECK-NEXT: store i32 0, ptr [[PTR:%.*]], align 4
@@ -334,7 +334,6 @@ define i32 @test9(i32 %b, ptr %ptr) {
; CHECK-NEXT: [[LOADED_SROA_SPECULATED:%.*]] = select i1 [[TEST]], i32 undef, i32 [[LOADED_SROA_SPECULATE_LOAD_FALSE]]
; CHECK-NEXT: ret i32 [[LOADED_SROA_SPECULATED]]
;
-
entry:
%f = alloca float
store i32 0, ptr %ptr
@@ -348,6 +347,7 @@ define float @test10(i32 %b, ptr %ptr) {
; Don't try to promote allocas which are not elligible for it even after
; rewriting due to the necessity of inserting bitcasts when speculating a PHI
; node.
+;
; CHECK-LABEL: @test10(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[F:%.*]] = alloca double, align 8
@@ -364,7 +364,6 @@ define float @test10(i32 %b, ptr %ptr) {
; CHECK-NEXT: [[PHI_SROA_SPECULATED:%.*]] = phi float [ [[F_0_PHI_SROA_SPECULATE_LOAD_ELSE]], [[ELSE]] ], [ [[PHI_SROA_SPECULATE_LOAD_THEN]], [[THEN]] ]
; CHECK-NEXT: ret float [[PHI_SROA_SPECULATED]]
;
-
entry:
%f = alloca double
store double 0.0, ptr %f
@@ -385,6 +384,7 @@ exit:
define float @test11(i32 %b, ptr %ptr) {
; Same as @test10 but for a select rather than a PHI node.
+;
; CHECK-LABEL: @test11(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[F:%.*]] = alloca double, align 8
@@ -396,7 +396,6 @@ define float @test11(i32 %b, ptr %ptr) {
; CHECK-NEXT: [[LOADED_SROA_SPECULATED:%.*]] = select i1 [[TEST]], float [[F_0_LOADED_SROA_SPECULATE_LOAD_TRUE]], float [[LOADED_SROA_SPECULATE_LOAD_FALSE]]
; CHECK-NEXT: ret float [[LOADED_SROA_SPECULATED]]
;
-
entry:
%f = alloca double
store double 0.0, ptr %f
@@ -410,11 +409,11 @@ entry:
define i32 @test12(i32 %x, ptr %p, i1 %c1) {
; Ensure we don't crash or fail to nuke dead selects of allocas if no load is
; never found.
+;
; CHECK-LABEL: @test12(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret i32 [[X:%.*]]
;
-
entry:
%a = alloca i32
store i32 %x, ptr %a
@@ -426,6 +425,7 @@ entry:
define i32 @test13(i32 %x, ptr %p, i1 %c1) {
; Ensure we don't crash or fail to nuke dead phis of allocas if no load is ever
; found.
+;
; CHECK-LABEL: @test13(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
@@ -434,7 +434,6 @@ define i32 @test13(i32 %x, ptr %p, i1 %c1) {
; CHECK: exit:
; CHECK-NEXT: ret i32 [[X:%.*]]
;
-
entry:
%a = alloca i32
store i32 %x, ptr %a
@@ -453,6 +452,7 @@ define i32 @test14(i1 %b1, i1 %b2, ptr %ptr) {
; Check for problems when there are both selects and phis and one is
; speculatable toward promotion but the other is not. That should block all of
; the speculation.
+;
; CHECK-LABEL: @test14(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[F:%.*]] = alloca i32, align 4
@@ -474,7 +474,6 @@ define i32 @test14(i1 %b1, i1 %b2, ptr %ptr) {
; CHECK-NEXT: [[RESULT:%.*]] = add i32 [[F_LOADED]], [[G_LOADED]]
; CHECK-NEXT: ret i32 [[RESULT]]
;
-
entry:
%f = alloca i32
%g = alloca i32
@@ -502,6 +501,7 @@ exit:
define void @PR13905(i1 %c1, i1 %c2, i1 %c3) {
; Check a pattern where we have a chain of dead phi nodes to ensure they are
; deleted and promotion can proceed.
+;
; CHECK-LABEL: @PR13905(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[C1:%.*]], label [[LOOP1:%.*]], label [[EXIT:%.*]]
@@ -513,7 +513,6 @@ define void @PR13905(i1 %c1, i1 %c2, i1 %c3) {
; CHECK-NEXT: [[PHI2:%.*]] = phi ptr [ poison, [[LOOP2]] ], [ null, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret void
;
-
entry:
%h = alloca i32
store i32 0, ptr %h
@@ -535,6 +534,7 @@ define i32 @PR13906(i1 %c1, i1 %c2) {
; Another pattern which can lead to crashes due to failing to clear out dead
; PHI nodes or select nodes. This triggers subtly
diff erently from the above
; cases because the PHI node is (recursively) alive, but the select is dead.
+;
; CHECK-LABEL: @PR13906(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_COND:%.*]]
@@ -543,7 +543,6 @@ define i32 @PR13906(i1 %c1, i1 %c2) {
; CHECK: if.then:
; CHECK-NEXT: br label [[FOR_COND]]
;
-
entry:
%c = alloca i32
store i32 0, ptr %c
@@ -559,6 +558,13 @@ if.then:
}
define i64 @PR14132(i1 %flag) {
+; Here we form a PHI-node by promoting the pointer alloca first, and then in
+; order to promote the other two allocas, we speculate the load of the
+; now-phi-node-pointer. In doing so we end up loading a 64-bit value from an i8
+; alloca. While this is a bit dubious, we were asserting on trying to
+; rewrite it. The trick is that the code using the value may carefully take
+; steps to only use the not-undef bits, and so we need to at least loosely
+; support this..
; CHECK-LABEL: @PR14132(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[FLAG:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
@@ -569,13 +575,6 @@ define i64 @PR14132(i1 %flag) {
; CHECK-NEXT: [[PTR_0_SROA_SPECULATED:%.*]] = phi i64 [ [[B_0_LOAD_EXT]], [[IF_THEN]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret i64 [[PTR_0_SROA_SPECULATED]]
;
-; Here we form a PHI-node by promoting the pointer alloca first, and then in
-; order to promote the other two allocas, we speculate the load of the
-; now-phi-node-pointer. In doing so we end up loading a 64-bit value from an i8
-; alloca. While this is a bit dubious, we were asserting on trying to
-; rewrite it. The trick is that the code using the value may carefully take
-; steps to only use the not-undef bits, and so we need to at least loosely
-; support this..
entry:
%a = alloca i64, align 8
%b = alloca i8, align 8
@@ -598,6 +597,9 @@ if.end:
}
define float @PR16687(i64 %x, i1 %flag) {
+; Check that even when we try to speculate the same phi twice (in two slices)
+; on an otherwise promotable construct, we don't get ahead of ourselves and try
+; to promote one of the slices prior to speculating it.
; CHECK-LABEL: @PR16687(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0_0_EXTRACT_TRUNC:%.*]] = trunc i64 [[X:%.*]] to i32
@@ -614,10 +616,6 @@ define float @PR16687(i64 %x, i1 %flag) {
; CHECK-NEXT: [[A_PHI_F_SROA_SPECULATED:%.*]] = phi float [ [[TMP0]], [[THEN]] ], [ [[TMP1]], [[ELSE]] ]
; CHECK-NEXT: ret float [[A_PHI_F_SROA_SPECULATED]]
;
-; Check that even when we try to speculate the same phi twice (in two slices)
-; on an otherwise promotable construct, we don't get ahead of ourselves and try
-; to promote one of the slices prior to speculating it.
-
entry:
%a = alloca i64, align 8
store i64 %x, ptr %a
diff --git a/llvm/test/Transforms/SROA/phi-catchswitch.ll b/llvm/test/Transforms/SROA/phi-catchswitch.ll
index 751e2475f220..ea90101883a6 100644
--- a/llvm/test/Transforms/SROA/phi-catchswitch.ll
+++ b/llvm/test/Transforms/SROA/phi-catchswitch.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=sroa -S | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
@@ -9,17 +10,37 @@ declare void @foo()
; Tests if the SROA pass correctly bails out on rewriting PHIs in a catchswitch
; BB.
-; CHECK-LABEL: @test_phi_catchswitch
define void @test_phi_catchswitch() personality ptr @__gxx_wasm_personality_v0 {
+; CHECK-LABEL: @test_phi_catchswitch(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP:%.*]] = alloca [[STRUCT_FOO:%.*]], align 4
+; CHECK-NEXT: invoke void @foo()
+; CHECK-NEXT: to label [[BB3:%.*]] unwind label [[BB10:%.*]]
+; CHECK: bb3:
+; CHECK-NEXT: invoke void @foo()
+; CHECK-NEXT: to label [[BB9:%.*]] unwind label [[CATCH_DISPATCH:%.*]]
+; CHECK: catch.dispatch:
+; CHECK-NEXT: [[TMP5:%.*]] = phi ptr [ [[TMP]], [[BB3]] ]
+; CHECK-NEXT: [[TMP6:%.*]] = catchswitch within none [label %catch.start] unwind label [[BB10]]
+; CHECK: catch.start:
+; CHECK-NEXT: [[TMP8:%.*]] = catchpad within [[TMP6]] [ptr null]
+; CHECK-NEXT: unreachable
+; CHECK: bb9:
+; CHECK-NEXT: unreachable
+; CHECK: bb10:
+; CHECK-NEXT: [[TMP11:%.*]] = phi ptr [ [[TMP]], [[ENTRY:%.*]] ], [ [[TMP5]], [[CATCH_DISPATCH]] ]
+; CHECK-NEXT: [[TMP12:%.*]] = cleanuppad within none []
+; CHECK-NEXT: store i32 0, ptr [[TMP11]], align 4
+; CHECK-NEXT: unreachable
+;
entry:
- ; CHECK: alloca
%tmp = alloca %struct.foo, align 4
invoke void @foo()
- to label %bb3 unwind label %bb10
+ to label %bb3 unwind label %bb10
bb3: ; preds = %entry
invoke void @foo()
- to label %bb9 unwind label %catch.dispatch
+ to label %bb9 unwind label %catch.dispatch
catch.dispatch: ; preds = %bb3
; While rewriting the alloca in the entry BB, the SROA pass tries to insert a
diff --git a/llvm/test/Transforms/SROA/ppcf128-no-fold.ll b/llvm/test/Transforms/SROA/ppcf128-no-fold.ll
index e38138e8d3de..b4a709018af7 100644
--- a/llvm/test/Transforms/SROA/ppcf128-no-fold.ll
+++ b/llvm/test/Transforms/SROA/ppcf128-no-fold.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=sroa -S | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
@@ -6,6 +7,15 @@ target triple = "powerpc64-unknown-linux-gnu"
declare void @bar(ptr, [2 x i128])
define void @foo(ptr %v) #0 {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast ppc_fp128 0xM403B0000000000000000000000000000 to i128
+; CHECK-NEXT: [[DOTFCA_0_INSERT:%.*]] = insertvalue [2 x i128] poison, i128 [[TMP0]], 0
+; CHECK-NEXT: [[TMP1:%.*]] = bitcast ppc_fp128 0xM4093B400000000000000000000000000 to i128
+; CHECK-NEXT: [[DOTFCA_1_INSERT:%.*]] = insertvalue [2 x i128] [[DOTFCA_0_INSERT]], i128 [[TMP1]], 1
+; CHECK-NEXT: call void @bar(ptr [[V:%.*]], [2 x i128] [[DOTFCA_1_INSERT]])
+; CHECK-NEXT: ret void
+;
entry:
%v.addr = alloca ptr, align 8
%z = alloca %struct.ld2, align 16
@@ -19,13 +29,6 @@ entry:
ret void
}
-; CHECK-LABEL: @foo
-; CHECK-NOT: i128 4628293042053316608
-; CHECK-NOT: i128 4653260752096854016
-; CHECK-DAG: bitcast ppc_fp128 0xM403B0000000000000000000000000000 to i128
-; CHECK-DAG: bitcast ppc_fp128 0xM4093B400000000000000000000000000 to i128
-; CHECK: call void @bar(ptr %v, [2 x i128]
-; CHECK: ret void
attributes #0 = { nounwind }
diff --git a/llvm/test/Transforms/SROA/pr26972.ll b/llvm/test/Transforms/SROA/pr26972.ll
index bb6f4a779b99..a0e620487392 100644
--- a/llvm/test/Transforms/SROA/pr26972.ll
+++ b/llvm/test/Transforms/SROA/pr26972.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=sroa -S | FileCheck %s
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-pc-linux"
@@ -5,9 +6,10 @@ target triple = "x86_64-pc-linux"
; Make sure we properly handle allocas where the allocated
; size overflows a uint32_t. This specific constant results in
; the size in bits being 32 after truncation to a 32-bit int.
-; CHECK-LABEL: fn1
-; CHECK-NEXT: ret void
define void @fn1() {
+; CHECK-LABEL: @fn1(
+; CHECK-NEXT: ret void
+;
%a = alloca [1073741825 x i32], align 16
call void @llvm.lifetime.end.p0(i64 4294967300, ptr %a)
ret void
diff --git a/llvm/test/Transforms/SROA/pr37267.ll b/llvm/test/Transforms/SROA/pr37267.ll
index 633ffcccc698..f78375885fc5 100644
--- a/llvm/test/Transforms/SROA/pr37267.ll
+++ b/llvm/test/Transforms/SROA/pr37267.ll
@@ -12,7 +12,6 @@ define i16 @f1() {
; CHECK-NEXT: [[RC:%.*]] = add i16 2, 2
; CHECK-NEXT: ret i16 [[RC]]
;
-
bb1:
; This 12-byte alloca is split into partitions as [0,2), [2,4), [4,8), [8,10), [10, 12).
; The reported error happened when rewriteIntegerStore try to widen a split tail of slice 1 for [4, 8) partition.
@@ -53,7 +52,6 @@ define i16 @f2() {
; CHECK-NEXT: [[RC:%.*]] = add i16 2, undef
; CHECK-NEXT: ret i16 [[RC]]
;
-
bb1:
; This 12-byte alloca is split into partitions as [0,2), [2,4), [4,8), [8,10), [10, 12).
; The reported error happened when visitLoadInst rewrites a split tail of slice 1 for [4, 8) partition.
diff --git a/llvm/test/Transforms/SROA/preserve-nonnull.ll b/llvm/test/Transforms/SROA/preserve-nonnull.ll
index effb0852ffbb..b5b885c57c40 100644
--- a/llvm/test/Transforms/SROA/preserve-nonnull.ll
+++ b/llvm/test/Transforms/SROA/preserve-nonnull.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=sroa -S | FileCheck %s
;
; Make sure that SROA doesn't lose nonnull metadata
@@ -7,12 +8,13 @@ declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture reado
; Check that we do basic propagation of nonnull when rewriting.
define ptr @propagate_nonnull(ptr %v) {
-; CHECK-LABEL: define ptr @propagate_nonnull(
+; CHECK-LABEL: @propagate_nonnull(
; CHECK-NEXT: entry:
-; CHECK-NEXT: %[[A:.*]] = alloca ptr
-; CHECK-NEXT: store ptr %v, ptr %[[A]]
-; CHECK-NEXT: %[[LOAD:.*]] = load volatile ptr, ptr %[[A]], align 8, !nonnull !0
-; CHECK-NEXT: ret ptr %[[LOAD]]
+; CHECK-NEXT: [[A_SROA_1:%.*]] = alloca ptr, align 8
+; CHECK-NEXT: store ptr [[V:%.*]], ptr [[A_SROA_1]], align 8
+; CHECK-NEXT: [[A_SROA_1_0_A_SROA_1_8_LOAD:%.*]] = load volatile ptr, ptr [[A_SROA_1]], align 8, !nonnull !0
+; CHECK-NEXT: ret ptr [[A_SROA_1_0_A_SROA_1_8_LOAD]]
+;
entry:
%a = alloca [2 x ptr]
%a.gep1 = getelementptr [2 x ptr], ptr %a, i32 0, i32 1
@@ -23,12 +25,13 @@ entry:
}
define ptr @turn_nonnull_into_assume(ptr %arg) {
-; CHECK-LABEL: define ptr @turn_nonnull_into_assume(
+; CHECK-LABEL: @turn_nonnull_into_assume(
; CHECK-NEXT: entry:
-; CHECK-NEXT: %[[RETURN:.*]] = load ptr, ptr %arg, align 8
-; CHECK-NEXT: %[[ASSUME:.*]] = icmp ne ptr %[[RETURN]], null
-; CHECK-NEXT: call void @llvm.assume(i1 %[[ASSUME]])
-; CHECK-NEXT: ret ptr %[[RETURN]]
+; CHECK-NEXT: [[BUF_0_COPYLOAD:%.*]] = load ptr, ptr [[ARG:%.*]], align 8
+; CHECK-NEXT: [[TMP0:%.*]] = icmp ne ptr [[BUF_0_COPYLOAD]], null
+; CHECK-NEXT: call void @llvm.assume(i1 [[TMP0]])
+; CHECK-NEXT: ret ptr [[BUF_0_COPYLOAD]]
+;
entry:
%buf = alloca ptr
call void @llvm.memcpy.p0.p0.i64(ptr align 8 %buf, ptr align 8 %arg, i64 8, i1 false)
@@ -43,12 +46,13 @@ entry:
; *does* initially, but then we lose that !range metadata before we finish
; SROA.
define ptr @propagate_nonnull_to_int() {
-; CHECK-LABEL: define ptr @propagate_nonnull_to_int(
+; CHECK-LABEL: @propagate_nonnull_to_int(
; CHECK-NEXT: entry:
-; CHECK-NEXT: %[[A:.*]] = alloca ptr
-; CHECK-NEXT: store ptr inttoptr (i64 42 to ptr), ptr %[[A]]
-; CHECK-NEXT: %[[LOAD:.*]] = load volatile ptr, ptr %[[A]]
-; CHECK-NEXT: ret ptr %[[LOAD]]
+; CHECK-NEXT: [[A_SROA_1:%.*]] = alloca ptr, align 8
+; CHECK-NEXT: store ptr inttoptr (i64 42 to ptr), ptr [[A_SROA_1]], align 8
+; CHECK-NEXT: [[A_SROA_1_0_A_SROA_1_8_LOAD:%.*]] = load volatile ptr, ptr [[A_SROA_1]], align 8, !nonnull !0
+; CHECK-NEXT: ret ptr [[A_SROA_1_0_A_SROA_1_8_LOAD]]
+;
entry:
%a = alloca [2 x ptr]
%a.gep1 = getelementptr [2 x ptr], ptr %a, i32 0, i32 1
@@ -63,9 +67,10 @@ entry:
; register. This can fail in interesting ways due to the rewrite iteration of
; SROA, resulting in PR32902.
define ptr @propagate_nonnull_to_int_and_promote() {
-; CHECK-LABEL: define ptr @propagate_nonnull_to_int_and_promote(
+; CHECK-LABEL: @propagate_nonnull_to_int_and_promote(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret ptr inttoptr (i64 42 to ptr)
+;
entry:
%a = alloca [2 x ptr], align 8
%a.gep1 = getelementptr [2 x ptr], ptr %a, i32 0, i32 1
diff --git a/llvm/test/Transforms/SROA/select-gep.ll b/llvm/test/Transforms/SROA/select-gep.ll
index 4309ad1405f6..9586feb8b160 100644
--- a/llvm/test/Transforms/SROA/select-gep.ll
+++ b/llvm/test/Transforms/SROA/select-gep.ll
@@ -52,10 +52,10 @@ define i32 @test_sroa_select_gep_volatile_load(i1 %cond) {
; CHECK-NEXT: store i32 12, ptr [[B_SROA_0]], align 4
; CHECK-NEXT: store i32 21, ptr [[A_SROA_2]], align 4
; CHECK-NEXT: store i32 22, ptr [[B_SROA_2]], align 4
-; CHECK-NEXT: [[SELECT_SROA_SEL:%.*]] = select i1 [[COND:%.*]], ptr [[A_SROA_0]], ptr [[B_SROA_0]]
-; CHECK-NEXT: [[LOAD1:%.*]] = load volatile i32, ptr [[SELECT_SROA_SEL]], align 4
-; CHECK-NEXT: [[SELECT_SROA_SEL3:%.*]] = select i1 [[COND]], ptr [[A_SROA_2]], ptr [[B_SROA_2]]
-; CHECK-NEXT: [[LOAD2:%.*]] = load volatile i32, ptr [[SELECT_SROA_SEL3]], align 4
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND:%.*]], ptr [[A_SROA_0]], ptr [[B_SROA_0]]
+; CHECK-NEXT: [[LOAD1:%.*]] = load volatile i32, ptr [[SELECT]], align 4
+; CHECK-NEXT: [[SELECT_SROA_SEL:%.*]] = select i1 [[COND]], ptr [[A_SROA_2]], ptr [[B_SROA_2]]
+; CHECK-NEXT: [[LOAD2:%.*]] = load volatile i32, ptr [[SELECT_SROA_SEL]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[LOAD1]], [[LOAD2]]
; CHECK-NEXT: ret i32 [[ADD]]
;
@@ -99,8 +99,8 @@ define i32 @test_sroa_gep_select_gep(i1 %cond) {
; CHECK-NEXT: [[B_SROA_0:%.*]] = alloca i32, align 4
; CHECK-NEXT: store i32 1, ptr [[A_SROA_0]], align 4
; CHECK-NEXT: store i32 2, ptr [[B_SROA_0]], align 4
-; CHECK-NEXT: [[SELECT_SROA_SEL:%.*]] = select i1 [[COND:%.*]], ptr [[A_SROA_0]], ptr [[B_SROA_0]]
-; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[COND]], ptr [[SELECT_SROA_SEL]], ptr [[A_SROA_0]]
+; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND:%.*]], ptr [[A_SROA_0]], ptr [[B_SROA_0]]
+; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[COND]], ptr [[SELECT]], ptr [[A_SROA_0]]
; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr [[SELECT2]], align 4
; CHECK-NEXT: ret i32 [[LOAD]]
;
diff --git a/llvm/test/Transforms/SROA/select-load.ll b/llvm/test/Transforms/SROA/select-load.ll
index c18ad6c5146d..75bcd346ef0a 100644
--- a/llvm/test/Transforms/SROA/select-load.ll
+++ b/llvm/test/Transforms/SROA/select-load.ll
@@ -152,7 +152,6 @@ entry:
!0 = !{!"branch_weights", i32 1, i32 99}
; Ensure that the branch metadata is reversed to match the reversals above.
-; CHECK: !0 = {{.*}} i32 1, i32 99}
declare void @llvm.lifetime.start.p0(i64, ptr )
declare void @llvm.lifetime.end.p0(i64, ptr)
diff --git a/llvm/test/Transforms/SROA/slice-order-independence.ll b/llvm/test/Transforms/SROA/slice-order-independence.ll
index 303f8b081f3c..47ac791ae56b 100644
--- a/llvm/test/Transforms/SROA/slice-order-independence.ll
+++ b/llvm/test/Transforms/SROA/slice-order-independence.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=sroa -S | FileCheck %s
target datalayout = "e-p:64:64:64-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
@@ -7,8 +8,16 @@ declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounw
; slices even in case of types that are skipped because their width is not a
; byte width multiple
define void @skipped_inttype_first(ptr) {
-; CHECK-LABEL: @skipped_inttype_first
-; CHECK: alloca ptr
+; CHECK-LABEL: @skipped_inttype_first(
+; CHECK-NEXT: [[ARG_SROA_0:%.*]] = alloca ptr, align 8
+; CHECK-NEXT: [[ARG_SROA_0_0_COPYLOAD:%.*]] = load ptr, ptr [[TMP0:%.*]], align 8
+; CHECK-NEXT: store ptr [[ARG_SROA_0_0_COPYLOAD]], ptr [[ARG_SROA_0]], align 8
+; CHECK-NEXT: [[ARG_SROA_3_0__SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 8
+; CHECK-NEXT: [[ARG_SROA_3_0_COPYLOAD:%.*]] = load i64, ptr [[ARG_SROA_3_0__SROA_IDX]], align 8
+; CHECK-NEXT: [[ARG_SROA_0_0_ARG_SROA_0_0_B0:%.*]] = load i63, ptr [[ARG_SROA_0]], align 8
+; CHECK-NEXT: [[ARG_SROA_0_0_ARG_SROA_0_0_B1:%.*]] = load ptr, ptr [[ARG_SROA_0]], align 8
+; CHECK-NEXT: ret void
+;
%arg = alloca { ptr, i32 }, align 8
call void @llvm.memcpy.p0.p0.i32(ptr align 8 %arg, ptr align 8 %0, i32 16, i1 false)
%b = getelementptr inbounds { ptr, i32 }, ptr %arg, i64 0, i32 0
@@ -18,8 +27,16 @@ define void @skipped_inttype_first(ptr) {
}
define void @skipped_inttype_last(ptr) {
-; CHECK-LABEL: @skipped_inttype_last
-; CHECK: alloca ptr
+; CHECK-LABEL: @skipped_inttype_last(
+; CHECK-NEXT: [[ARG_SROA_0:%.*]] = alloca ptr, align 8
+; CHECK-NEXT: [[ARG_SROA_0_0_COPYLOAD:%.*]] = load ptr, ptr [[TMP0:%.*]], align 8
+; CHECK-NEXT: store ptr [[ARG_SROA_0_0_COPYLOAD]], ptr [[ARG_SROA_0]], align 8
+; CHECK-NEXT: [[ARG_SROA_3_0__SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 8
+; CHECK-NEXT: [[ARG_SROA_3_0_COPYLOAD:%.*]] = load i64, ptr [[ARG_SROA_3_0__SROA_IDX]], align 8
+; CHECK-NEXT: [[ARG_SROA_0_0_ARG_SROA_0_0_B1:%.*]] = load ptr, ptr [[ARG_SROA_0]], align 8
+; CHECK-NEXT: [[ARG_SROA_0_0_ARG_SROA_0_0_B0:%.*]] = load i63, ptr [[ARG_SROA_0]], align 8
+; CHECK-NEXT: ret void
+;
%arg = alloca { ptr, i32 }, align 8
call void @llvm.memcpy.p0.p0.i32(ptr align 8 %arg, ptr align 8 %0, i32 16, i1 false)
%b = getelementptr inbounds { ptr, i32 }, ptr %arg, i64 0, i32 0
diff --git a/llvm/test/Transforms/SROA/tbaa-struct2.ll b/llvm/test/Transforms/SROA/tbaa-struct2.ll
index 1c81fc6163bb..484651ab0e48 100644
--- a/llvm/test/Transforms/SROA/tbaa-struct2.ll
+++ b/llvm/test/Transforms/SROA/tbaa-struct2.ll
@@ -34,12 +34,3 @@ define double @bar(ptr %wishart) {
!6 = !{!"Simple C++ TBAA"}
!7 = !{!8, !8, i64 0}
!8 = !{!"int", !5, i64 0}
-
-; CHECK: !0 = !{i64 0, i64 8, !1, i64 8, i64 4, !5}
-; CHECK: !1 = !{!2, !2, i64 0}
-; CHECK: !2 = !{!"double", !{{[0-9]+}}, i64 0}
-
-; CHECK: !5 = !{!6, !6, i64 0}
-; CHECK: !6 = !{!"int", !{{[0-9]+}}, i64 0}
-; CHECK: !7 = !{i64 0, i64 4, !5}
-; CHECK: !8 = !{}
diff --git a/llvm/test/Transforms/SROA/vector-lifetime-intrinsic.ll b/llvm/test/Transforms/SROA/vector-lifetime-intrinsic.ll
index 13ad8f7380c9..ad34b7b30c08 100644
--- a/llvm/test/Transforms/SROA/vector-lifetime-intrinsic.ll
+++ b/llvm/test/Transforms/SROA/vector-lifetime-intrinsic.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes=sroa -S < %s | FileCheck %s
target datalayout = "e-p:64:32-i64:32-v32:32-n32-S64"
@@ -8,10 +9,13 @@ declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #0
; Function Attrs: nounwind
declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #0
-; CHECK: @wombat
-; CHECK-NOT: alloca
-; CHECK: ret void
define void @wombat(<4 x float> %arg1) {
+; CHECK-LABEL: @wombat(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP_0_VEC_EXTRACT:%.*]] = shufflevector <4 x float> [[ARG1:%.*]], <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2>
+; CHECK-NEXT: call void @wombat3(<3 x float> [[TMP_0_VEC_EXTRACT]])
+; CHECK-NEXT: ret void
+;
bb:
%tmp = alloca <4 x float>, align 16
call void @llvm.lifetime.start.p0(i64 16, ptr %tmp)
diff --git a/llvm/test/Transforms/SROA/vector-promotion-
diff erent-size.ll b/llvm/test/Transforms/SROA/vector-promotion-
diff erent-size.ll
index d31ed11ac4b8..a410c8a5b633 100644
--- a/llvm/test/Transforms/SROA/vector-promotion-
diff erent-size.ll
+++ b/llvm/test/Transforms/SROA/vector-promotion-
diff erent-size.ll
@@ -9,7 +9,6 @@ define <4 x i1> @vector_bitcast() {
; CHECK-NEXT: [[A_0_VEC:%.*]] = load <4 x i1>, ptr [[A]], align 1
; CHECK-NEXT: ret <4 x i1> [[A_0_VEC]]
;
-
%a = alloca <3 x i1>
store <3 x i1> <i1 1,i1 0,i1 1>, ptr %a
%vec = load <4 x i1>, ptr %a
@@ -23,7 +22,6 @@ define <64 x i16> @vector_bitcast_2(<32 x i16> %v) {
; CHECK-NEXT: [[P_0_LOAD:%.*]] = load <64 x i16>, ptr [[P]], align 64
; CHECK-NEXT: ret <64 x i16> [[P_0_LOAD]]
;
-
%p = alloca <32 x i16>
store <32 x i16> %v, ptr %p
%load = load <64 x i16>, ptr %p
diff --git a/llvm/test/Transforms/SROA/vector-promotion.ll b/llvm/test/Transforms/SROA/vector-promotion.ll
index bdf50ea39af3..ec3c932e1b6b 100644
--- a/llvm/test/Transforms/SROA/vector-promotion.ll
+++ b/llvm/test/Transforms/SROA/vector-promotion.ll
@@ -175,6 +175,8 @@ entry:
}
define i32 @test5(<4 x i32> %x, <4 x i32> %y, ptr %z) {
+; The same as the above, but with reversed source and destination for the
+; element memcpy, and a self copy.
; CHECK-LABEL: @test5(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[Z_TMP1:%.*]] = getelementptr inbounds <4 x i32>, ptr [[Z:%.*]], i64 0, i64 2
@@ -187,8 +189,6 @@ define i32 @test5(<4 x i32> %x, <4 x i32> %y, ptr %z) {
; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[A_SROA_4_0_VEC_EXTRACT]], [[TMP4]]
; CHECK-NEXT: ret i32 [[TMP5]]
;
-; The same as the above, but with reversed source and destination for the
-; element memcpy, and a self copy.
entry:
%a = alloca [2 x <4 x i32>]
@@ -216,6 +216,8 @@ declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounw
declare void @llvm.memset.p0.i32(ptr nocapture, i8, i32, i1) nounwind
define i64 @test6(<4 x i64> %x, <4 x i64> %y, i64 %n) {
+; The old scalarrepl pass would wrongly drop the store to the second alloca.
+; PR13254
; CHECK-LABEL: @test6(
; CHECK-NEXT: [[TMP:%.*]] = alloca { <4 x i64>, <4 x i64> }, align 32
; CHECK-NEXT: [[P0:%.*]] = getelementptr inbounds { <4 x i64>, <4 x i64> }, ptr [[TMP]], i32 0, i32 0
@@ -226,8 +228,6 @@ define i64 @test6(<4 x i64> %x, <4 x i64> %y, i64 %n) {
; CHECK-NEXT: [[RES:%.*]] = load i64, ptr [[ADDR]], align 4
; CHECK-NEXT: ret i64 [[RES]]
;
-; The old scalarrepl pass would wrongly drop the store to the second alloca.
-; PR13254
%tmp = alloca { <4 x i64>, <4 x i64> }
%p0 = getelementptr inbounds { <4 x i64>, <4 x i64> }, ptr %tmp, i32 0, i32 0
store <4 x i64> %x, ptr %p0
@@ -363,6 +363,8 @@ entry:
}
define i32 @PR14212(<3 x i8> %val) {
+; This caused a crash when "splitting" the load of the i32 in order to promote
+; the store of <3 x i8> properly. Heavily reduced from an OpenCL test case.
; CHECK-LABEL: @PR14212(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <3 x i8> [[VAL:%.*]] to i24
@@ -375,8 +377,6 @@ define i32 @PR14212(<3 x i8> %val) {
; CHECK-NEXT: [[RETVAL_0_INSERT_INSERT:%.*]] = or i32 [[RETVAL_0_INSERT_MASK]], [[RETVAL_0_INSERT_EXT]]
; CHECK-NEXT: ret i32 [[RETVAL_0_INSERT_INSERT]]
;
-; This caused a crash when "splitting" the load of the i32 in order to promote
-; the store of <3 x i8> properly. Heavily reduced from an OpenCL test case.
entry:
%retval = alloca <3 x i8>, align 4
@@ -386,6 +386,9 @@ entry:
}
define <2 x i8> @PR14349.1(i32 %x) {
+; The first testcase for broken SROA rewriting of split integer loads and
+; stores due to smaller vector loads and stores. This particular test ensures
+; that we can rewrite a split store of an integer to a store of a vector.
; CHECK-LABEL: @PR14349.1(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[X:%.*]] to i16
@@ -394,9 +397,6 @@ define <2 x i8> @PR14349.1(i32 %x) {
; CHECK-NEXT: [[A_SROA_2_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[A_SROA_2_0_EXTRACT_SHIFT]] to i16
; CHECK-NEXT: ret <2 x i8> [[TMP0]]
;
-; The first testcase for broken SROA rewriting of split integer loads and
-; stores due to smaller vector loads and stores. This particular test ensures
-; that we can rewrite a split store of an integer to a store of a vector.
entry:
%a = alloca i32
@@ -408,6 +408,9 @@ entry:
}
define i32 @PR14349.2(<2 x i8> %x) {
+; The first testcase for broken SROA rewriting of split integer loads and
+; stores due to smaller vector loads and stores. This particular test ensures
+; that we can rewrite a split load of an integer to a load of a vector.
; CHECK-LABEL: @PR14349.2(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i8> [[X:%.*]] to i16
@@ -420,9 +423,6 @@ define i32 @PR14349.2(<2 x i8> %x) {
; CHECK-NEXT: [[A_SROA_0_0_INSERT_INSERT:%.*]] = or i32 [[A_SROA_0_0_INSERT_MASK]], [[A_SROA_0_0_INSERT_EXT]]
; CHECK-NEXT: ret i32 [[A_SROA_0_0_INSERT_INSERT]]
;
-; The first testcase for broken SROA rewriting of split integer loads and
-; stores due to smaller vector loads and stores. This particular test ensures
-; that we can rewrite a split load of an integer to a load of a vector.
entry:
%a = alloca i32
@@ -435,6 +435,7 @@ entry:
define i32 @test7(<2 x i32> %x, <2 x i32> %y) {
; Test that we can promote to vectors when the alloca doesn't mention any vector types.
+;
; CHECK-LABEL: @test7(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0_4_VEC_EXTRACT:%.*]] = extractelement <2 x i32> [[X:%.*]], i32 1
@@ -466,6 +467,7 @@ entry:
define i32 @test8(<2 x i32> %x) {
; Ensure that we can promote an alloca that doesn't mention a vector type based
; on a single store with a vector type.
+;
; CHECK-LABEL: @test8(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0_0_VEC_EXTRACT:%.*]] = extractelement <2 x i32> [[X:%.*]], i32 0
@@ -489,6 +491,7 @@ entry:
define <2 x i32> @test9(i32 %x, i32 %y) {
; Ensure that we can promote an alloca that doesn't mention a vector type based
; on a single load with a vector type.
+;
; CHECK-LABEL: @test9(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x i32> undef, i32 [[X:%.*]], i32 0
@@ -510,6 +513,7 @@ entry:
define <2 x i32> @test10(<4 x i16> %x, i32 %y) {
; If there are multiple
diff erent vector types used, we should select the one
; with the widest elements.
+;
; CHECK-LABEL: @test10(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[X:%.*]] to <2 x i32>
@@ -532,6 +536,7 @@ define <2 x float> @test11(<4 x i16> %x, i32 %y) {
; If there are multiple
diff erent element types for
diff erent vector types,
; pick the integer types. This isn't really important, but seems like the best
; heuristic for making a deterministic decision.
+;
; CHECK-LABEL: @test11(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[X:%.*]] to <2 x i32>
diff --git a/llvm/test/Transforms/SROA/vectors-of-pointers.ll b/llvm/test/Transforms/SROA/vectors-of-pointers.ll
index d22fd544a649..fedbfbeee8e8 100644
--- a/llvm/test/Transforms/SROA/vectors-of-pointers.ll
+++ b/llvm/test/Transforms/SROA/vectors-of-pointers.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=sroa
; Make sure we don't crash on this one.
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