[PATCH] D139037: [RISCV] Fold low 12 bits into instruction during frame index elimination

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:305
+      MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Lo12);
+      Offset = StackOffset::get(SignExtend64<32>(Hi20 << 12), Offset.getScalable());
     }
----------------
craig.topper wrote:
> Can this just be
> 
> `SignExtend64<32>(Val - Lo12)`?
See comment about being really bad at bitmath.  I tried to follow the constant materialization code as closely as possible.  :)

If you think this is correct, I'll make the change and report any differences I spot.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139037/new/

https://reviews.llvm.org/D139037