[PATCH] D139037: [RISCV] Fold low 12 bits into instruction during frame index elimination

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:305
+      MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Lo12);
+      Offset = StackOffset::get(SignExtend64<32>(Hi20 << 12), Offset.getScalable());
     }
----------------
Can this just be

`SignExtend64<32>(Val - Lo12)`?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139037/new/

https://reviews.llvm.org/D139037