[llvm] 7fea6f2 - [AArch64] Assembly support for VMSA
Tomas Matheson via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 30 05:37:44 PST 2022
Author: Tomas Matheson
Date: 2022-11-30T13:37:02Z
New Revision: 7fea6f2e0e606e5339c3359568f680eaf64aa306
URL: https://github.com/llvm/llvm-project/commit/7fea6f2e0e606e5339c3359568f680eaf64aa306
DIFF: https://github.com/llvm/llvm-project/commit/7fea6f2e0e606e5339c3359568f680eaf64aa306.diff
LOG: [AArch64] Assembly support for VMSA
Virtual Memory System Architecture (VMSA)
This is part of the 2022 A-Profile Architecture extensions and adds support for
the following:
- Translation Hardening Extension (FEAT_THE)
- 128-bit Page Table Descriptors (FEAT_D128)
- 56-bit Virtual Address (FEAT_LVA3)
- Support for 128-bit System Registers (FEAT_SYSREG128)
- System Instructions that can take 128-bit inputs (FEAT_SYSINSTR128)
- 128-bit Atomic Instructions (FEAT_LSE128)
- Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE)
- Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE)
- Memory Attribute Index Enhancement (FEAT_AIE)
New instructions added:
- FEAT_SYSREG128 adds MRRS and MSRR.
- FEAT_SYSINSTR128 adds the SYSP instruction and TLBIP aliases.
- FEAT_LSE128 adds LDCLRP, LDSET, and SWPP instructions.
- FEAT_THE adds the set of RCW* instructions.
Specs for individual instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/
Contributors:
Keith Walker
Lucas Prates
Sam Elliott
Son Tuan Vu
Tomas Matheson
Differential Revision: https://reviews.llvm.org/D138920
Added:
clang/test/Driver/aarch64-d128.c
clang/test/Driver/aarch64-lse128.c
clang/test/Driver/aarch64-the.c
llvm/test/MC/AArch64/armv8.9a-the.s
llvm/test/MC/AArch64/armv9-mrrs.s
llvm/test/MC/AArch64/armv9-msrr.s
llvm/test/MC/AArch64/armv9-sysp.s
llvm/test/MC/AArch64/armv9.4-lse128.s
llvm/test/MC/Disassembler/AArch64/armv8.9a-the.txt
llvm/test/MC/Disassembler/AArch64/armv9-sysp.txt
llvm/test/MC/Disassembler/AArch64/armv9-sysreg128.txt
llvm/test/MC/Disassembler/AArch64/armv9.4a-lse128.txt
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td
llvm/lib/Target/AArch64/AArch64SystemOperands.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
llvm/test/MC/AArch64/arm64-system-encoding.s
llvm/test/MC/AArch64/basic-a64-instructions.s
llvm/test/MC/AArch64/directive-arch_extension-negative.s
llvm/test/MC/AArch64/directive-arch_extension.s
llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
llvm/unittests/Support/TargetParserTest.cpp
Removed:
################################################################################
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index 1221b84676d9b..fb3d0b553542a 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -461,6 +461,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
if (HasMOPS)
Builder.defineMacro("__ARM_FEATURE_MOPS", "1");
+ if (HasD128)
+ Builder.defineMacro("__ARM_FEATURE_SYSREG128", "1");
+
switch (ArchKind) {
default:
break;
@@ -596,6 +599,7 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasMatmulFP32 = false;
HasLSE = false;
HasMOPS = false;
+ HasD128 = false;
HasRCPC = false;
ArchKind = llvm::AArch64::ArchKind::INVALID;
@@ -719,6 +723,16 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasFlagM = true;
if (Feature == "+mops")
HasMOPS = true;
+ if (Feature == "+d128")
+ HasD128 = true;
+ }
+
+ // Check features that are manually disabled by command line options.
+ // This needs to be checked after architecture-related features are handled,
+ // making sure they are properly disabled when required.
+ for (const auto &Feature : Features) {
+ if (Feature == "-d128")
+ HasD128 = false;
}
setDataLayout();
diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h
index 6d2eb866444d4..1791e462139f3 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -53,6 +53,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
bool HasLSE;
bool HasFlagM;
bool HasMOPS;
+ bool HasD128;
bool HasRCPC;
llvm::AArch64::ArchKind ArchKind;
diff --git a/clang/test/Driver/aarch64-d128.c b/clang/test/Driver/aarch64-d128.c
new file mode 100644
index 0000000000000..28305dad00e3a
--- /dev/null
+++ b/clang/test/Driver/aarch64-d128.c
@@ -0,0 +1,10 @@
+// Test that target feature d128 is implemented and available correctly
+
+// FEAT_D128 is optional (off by default) for v9.4a and older, and can be enabled using +d128
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+d128 %s 2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+nod128 %s 2>&1 | FileCheck %s --check-prefix=DISABLED
+
+// ENABLED: "-target-feature" "+d128"
+// NOT_ENABLED-NOT: "-target-feature" "+d128"
+// DISABLED: "-target-feature" "-d128"
diff --git a/clang/test/Driver/aarch64-lse128.c b/clang/test/Driver/aarch64-lse128.c
new file mode 100644
index 0000000000000..1feb0a58d9c9e
--- /dev/null
+++ b/clang/test/Driver/aarch64-lse128.c
@@ -0,0 +1,10 @@
+// Test that target feature lse128 is implemented and available correctly
+
+// FEAT_LSE128 is optional (off by default) for v9.4a and older, and can be enabled using +lse128
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+lse128 %s 2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+nolse128 %s 2>&1 | FileCheck %s --check-prefix=DISABLED
+
+// ENABLED: "-target-feature" "+lse128"
+// NOT_ENABLED-NOT: "-target-feature" "+lse128"
+// DISABLED: "-target-feature" "-lse128"
diff --git a/clang/test/Driver/aarch64-the.c b/clang/test/Driver/aarch64-the.c
new file mode 100644
index 0000000000000..0ec053c50cbe0
--- /dev/null
+++ b/clang/test/Driver/aarch64-the.c
@@ -0,0 +1,26 @@
+// Test that target feature the is implemented and available correctly
+
+// FEAT_THE is optional (off by default) for v8.9a/9.4a, and can be disabled using +nothe
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a+the %s 2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a+nothe %s 2>&1 | FileCheck %s --check-prefix=DISABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+the %s 2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+nothe %s 2>&1 | FileCheck %s --check-prefix=DISABLED
+
+// FEAT_THE is optional (off by default) for v8.8a/9.3a and older, and can be enabled using +the
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+the %s 2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+nothe %s 2>&1 | FileCheck %s --check-prefix=DISABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+the %s 2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+nothe %s 2>&1 | FileCheck %s --check-prefix=DISABLED
+
+// FEAT_THE is invalid before v8
+// RUN: %clang -### -target arm-none-none-eabi -march=armv7-a+the %s 2>&1 | FileCheck %s --check-prefix=INVALID
+
+// INVALID: error: unsupported argument 'armv7-a+the' to option '-march='
+// ENABLED: "-target-feature" "+the"
+// NOT_ENABLED-NOT: "-target-feature" "+the"
+// DISABLED: "-target-feature" "-the"
+
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def b/llvm/include/llvm/Support/AArch64TargetParser.def
index 6fd68872e96c1..d522bbfbd2359 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.def
+++ b/llvm/include/llvm/Support/AArch64TargetParser.def
@@ -153,6 +153,9 @@ AARCH64_ARCH_EXT_NAME("mops", AArch64::AEK_MOPS, "+mops",
AARCH64_ARCH_EXT_NAME("pmuv3", AArch64::AEK_PERFMON, "+perfmon", "-perfmon")
AARCH64_ARCH_EXT_NAME("cssc", AArch64::AEK_CSSC, "+cssc", "-cssc")
AARCH64_ARCH_EXT_NAME("rcpc3", AArch64::AEK_RCPC3, "+rcpc3", "-rcpc3")
+AARCH64_ARCH_EXT_NAME("the", AArch64::AEK_THE, "+the", "-the")
+AARCH64_ARCH_EXT_NAME("d128", AArch64::AEK_D128, "+d128", "-d128")
+AARCH64_ARCH_EXT_NAME("lse128", AArch64::AEK_LSE128, "+lse128", "-lse128")
#undef AARCH64_ARCH_EXT_NAME
#ifndef AARCH64_CPU_NAME
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.h b/llvm/include/llvm/Support/AArch64TargetParser.h
index 3261e3f5b5eae..e937b563ee631 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.h
+++ b/llvm/include/llvm/Support/AArch64TargetParser.h
@@ -78,6 +78,9 @@ enum ArchExtKind : uint64_t {
AEK_SMEF16F16 = 1ULL << 47, // FEAT_SMEF16F16
AEK_CSSC = 1ULL << 48, // FEAT_CSSC
AEK_RCPC3 = 1ULL << 49, // FEAT_LRCPC3
+ AEK_THE = 1ULL << 50, // FEAT_THE
+ AEK_D128 = 1ULL << 51, // FEAT_D128
+ AEK_LSE128 = 1ULL << 52, // FEAT_LSE128
};
enum class ArchKind {
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 1fedf5b770b62..a9c2509605d7f 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -515,6 +515,20 @@ def FeatureRCPC3 : SubtargetFeature<"rcpc3", "HasRCPC3",
"true", "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set (FEAT_LRCPC3)",
[FeatureRCPC_IMMO]>;
+def FeatureTHE : SubtargetFeature<"the", "HasTHE",
+ "true", "Enable Armv8.9-A Translation Hardening Extension (FEAT_THE)">;
+
+def FeatureLSE128 : SubtargetFeature<"lse128", "HasLSE128",
+ "true", "Enable Armv9.4-A 128-bit Atomic Instructions (FEAT_LSE128)",
+ [FeatureLSE]>;
+
+// FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, and FEAT_SYSINSTR128 are mutually implicit.
+// Therefore group them all under a single feature flag, d128:
+def FeatureD128 : SubtargetFeature<"d128", "HasD128",
+ "true", "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers "
+ "and Instructions (FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128)",
+ [FeatureLSE128]>;
+
//===----------------------------------------------------------------------===//
// Architectures.
//
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 319cedc228c5a..ee3761fcf0a17 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -11842,6 +11842,247 @@ def TRCIT : RtSystemI<0b0, (outs), (ins GPR64:$Rt), "trcit", "\t$Rt"> {
let Inst{7-5} = 0b111;
}
+// * RCWCAS family
+// * RCW<OP> family
+
+//--------------------------------------------------------------------
+// Read-Check-Write Compare And Swap family (RCWCAS[S|P|PS]?[A|L|AL]?)
+
+// Instruction encoding:
+//
+// 31 30|29 24|23|22|21|20 16|15|14 13|12 11 10|9 5|4 0
+// RCWCAS 0 0|011001| A| R| 1| Rs| 0| 0 0| 0 1 0| Rn| Rt
+// RCWSCAS 0 1|011001| A| R| 1| Rs| 0| 0 0| 0 1 0| Rn| Rt
+// RCWCASP 0 0|011001| A| R| 1| Rs| 0| 0 0| 0 1 1| Rn| Rt
+// RCWSCASP 0 1|011001| A| R| 1| Rs| 0| 0 0| 0 1 1| Rn| Rt
+
+// Instruction syntax:
+//
+// RCW[S]CAS{<order>} <Xs>, <Xt>, [<Xn|SP>]
+// RCW[S]CASP{<order>} <Xs>, <X(s+1)>, <Xt>, <X(t+1)> [<Xn|SP>]
+
+class BaseRCWCASEncoding<dag oops, dag iops, string asm>
+ : I<oops, iops, asm, "\t$Rs, $Rt, [$Rn]", "$out = $Rs", []>,
+ Sched<[]> {
+ bit Acq;
+ bit Rel;
+ bit SC;
+ bit Pair;
+ bits<5> Rs;
+ bits<5> Rn;
+ bits<5> Rt;
+ let Inst{31} = 0b0;
+ let Inst{30} = SC;
+ let Inst{29-24} = 0b011001;
+ let Inst{23} = Acq;
+ let Inst{22} = Rel;
+ let Inst{21} = 0b1;
+ let Inst{20-16} = Rs;
+ let Inst{15-13} = 0b000;
+ let Inst{12-11} = 0b01;
+ let Inst{10} = Pair;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Rt;
+ let mayLoad = 1;
+ let mayStore = 1;
+ let hasSideEffects = 1;
+ let Defs = [NZCV];
+}
+
+multiclass BaseRCWCAS<dag oops, dag iops, string prefix> {
+ let Acq = 0b0, Rel = 0b0 in
+ def "" : BaseRCWCASEncoding<oops, iops, prefix # "">;
+ let Acq = 0b1, Rel = 0b0 in
+ def A : BaseRCWCASEncoding<oops, iops, prefix # "a">;
+ let Acq = 0b0, Rel = 0b1 in
+ def L : BaseRCWCASEncoding<oops, iops, prefix # "l">;
+ let Acq = 0b1, Rel = 0b1 in
+ def AL : BaseRCWCASEncoding<oops, iops, prefix # "al">;
+}
+
+multiclass ReadCheckWriteCompareAndSwap {
+ let SC = 0b0, Pair = 0b0, Predicates = [HasTHE] in
+ defm CAS : BaseRCWCAS<(outs GPR64:$out),
+ (ins GPR64:$Rs, GPR64:$Rt, GPR64sp:$Rn), "rcwcas" >;
+ let SC = 0b1, Pair = 0b0, Predicates = [HasTHE] in
+ defm SCAS : BaseRCWCAS<(outs GPR64:$out),
+ (ins GPR64:$Rs, GPR64:$Rt, GPR64sp:$Rn), "rcwscas">;
+ let SC = 0b0, Pair = 0b1, Predicates = [HasTHE, HasD128] in
+ defm CASP : BaseRCWCAS<(outs XSeqPairClassOperand:$out),
+ (ins XSeqPairClassOperand:$Rs,
+ XSeqPairClassOperand:$Rt, GPR64sp:$Rn),
+ "rcwcasp">;
+ let SC = 0b1, Pair = 0b1, Predicates = [HasTHE, HasD128] in
+ defm SCASP: BaseRCWCAS<(outs XSeqPairClassOperand:$out),
+ (ins XSeqPairClassOperand:$Rs,
+ XSeqPairClassOperand:$Rt, GPR64sp:$Rn),
+ "rcwscasp">;
+}
+
+//------------------------------------------------------------------
+// Read-Check-Write <OP> family (RCW[CLR|SET|SWP][S|P|PS]?[A|L|AL]?)
+
+// Instruction encoding:
+//
+// 31 30|29 24|23|22|21|20 16|15|14 12|11 10|9 5|4 0
+// RCWCLR 0 0|111000| A| R| 1| Rs| 1| 001| 0 0| Rn| Rt
+// RCWSCLR 0 1|111000| A| R| 1| Rs| 1| 001| 0 0| Rn| Rt
+// RCWSET 0 0|111000| A| R| 1| Rs| 1| 011| 0 0| Rn| Rt
+// RCWSSET 0 1|111000| A| R| 1| Rs| 1| 011| 0 0| Rn| Rt
+// RCWSWP 0 0|111000| A| R| 1| Rs| 1| 010| 0 0| Rn| Rt
+// RCWSSWP 0 1|111000| A| R| 1| Rs| 1| 010| 0 0| Rn| Rt
+
+// 31 30|29 24|23|22|21|20 16|15|14 12|11 10|9 5|4 0
+// RCWCLRP 0 0|011001| A| R| 1| Rt2| 1| 001| 0 0| Rn| Rt
+// RCWSCLRP 0 1|011001| A| R| 1| Rt2| 1| 001| 0 0| Rn| Rt
+// RCWSETP 0 0|011001| A| R| 1| Rt2| 1| 011| 0 0| Rn| Rt
+// RCWSSETP 0 1|011001| A| R| 1| Rt2| 1| 011| 0 0| Rn| Rt
+// RCWSWPP 0 0|011001| A| R| 1| Rt2| 1| 010| 0 0| Rn| Rt
+// RCWSSWPP 0 1|011001| A| R| 1| Rt2| 1| 010| 0 0| Rn| Rt
+
+// Instruction syntax:
+//
+// RCW[S]<OP>{<order>} <Xs>, <Xt>, [<Xn|SP>]
+// RCW[S]<OP>P{<order>} <Xt1>, <Xt2>, [<Xn|SP>]
+
+class BaseRCWOPEncoding<string asm>
+ : I<(outs GPR64:$Rt),(ins GPR64:$Rs, GPR64sp:$Rn), asm,
+ "\t$Rs, $Rt, [$Rn]", "", []>,
+ Sched<[]> {
+ bit Acq;
+ bit Rel;
+ bit SC;
+ bits<3> opc;
+ bits<5> Rs;
+ bits<5> Rn;
+ bits<5> Rt;
+ let Inst{31} = 0b0;
+ let Inst{30} = SC;
+ let Inst{29-24} = 0b111000;
+ let Inst{23} = Acq;
+ let Inst{22} = Rel;
+ let Inst{21} = 0b1;
+ let Inst{20-16} = Rs;
+ let Inst{15} = 0b1;
+ let Inst{14-12} = opc;
+ let Inst{11-10} = 0b00;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Rt;
+ let mayLoad = 1;
+ let mayStore = 1;
+ let hasSideEffects = 1;
+ let Defs = [NZCV];
+ let Predicates = [HasTHE];
+}
+
+class BaseRCWOPPEncoding<string asm>
+ : I<(outs GPR64common:$Rt_wb, GPR64common:$Rt2_wb),
+ (ins GPR64common:$Rt, GPR64common:$Rt2, GPR64sp:$Rn), asm,
+ "\t$Rt, $Rt2, [$Rn]", "$Rt = $Rt_wb, $Rt2 = $Rt2_wb", []>,
+ Sched<[]> {
+ bit Acq;
+ bit Rel;
+ bit SC;
+ bits<3> opc;
+ bits<5> Rt2;
+ bits<5> Rn;
+ bits<5> Rt;
+ let Inst{31} = 0b0;
+ let Inst{30} = SC;
+ let Inst{29-24} = 0b011001;
+ let Inst{23} = Acq;
+ let Inst{22} = Rel;
+ let Inst{21} = 0b1;
+ let Inst{20-16} = Rt2;
+ let Inst{15} = 0b1;
+ let Inst{14-12} = opc;
+ let Inst{11-10} = 0b00;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Rt;
+ let mayLoad = 1;
+ let mayStore = 1;
+ let hasSideEffects = 1;
+ let Defs = [NZCV];
+ let Predicates = [HasTHE, HasD128];
+}
+
+multiclass BaseRCWOP<string prefix> {
+ let Acq = 0b0, Rel = 0b0 in def "" : BaseRCWOPEncoding<prefix # "">;
+ let Acq = 0b1, Rel = 0b0 in def A : BaseRCWOPEncoding<prefix # "a">;
+ let Acq = 0b0, Rel = 0b1 in def L : BaseRCWOPEncoding<prefix # "l">;
+ let Acq = 0b1, Rel = 0b1 in def AL : BaseRCWOPEncoding<prefix # "al">;
+
+ let Acq = 0b0, Rel = 0b0 in def P : BaseRCWOPPEncoding<prefix # "p">;
+ let Acq = 0b1, Rel = 0b0 in def PA : BaseRCWOPPEncoding<prefix # "pa">;
+ let Acq = 0b0, Rel = 0b1 in def PL : BaseRCWOPPEncoding<prefix # "pl">;
+ let Acq = 0b1, Rel = 0b1 in def PAL : BaseRCWOPPEncoding<prefix # "pal">;
+}
+
+multiclass ReadCheckWriteOperation<bits<3> opc, string op> {
+ let SC = 0b0, opc = opc in defm "" : BaseRCWOP<"rcw" # "" # op>;
+ let SC = 0b1, opc = opc in defm S : BaseRCWOP<"rcw" # "s" # op >;
+}
+
+//---
+// 128-bit atomic instructions (FEAT_LSE128)
+//---
+
+let mayLoad = 1, mayStore = 1, hasSideEffects = 0 in
+class LSE128Base<bits<3> op0, bits<2> AR, bit o3, string asm>
+: I<(outs GPR64common:$Rt_wb, GPR64common:$Rt2_wb),
+ (ins GPR64common:$Rt, GPR64common:$Rt2, GPR64sp:$Rn),
+ asm, "\t$Rt, $Rt2, [$Rn]",
+ "$Rt = $Rt_wb, $Rt2 = $Rt2_wb", []>,
+ Sched<[]> {
+ bits<5> Rt;
+ bits<5> Rt2;
+ bits<5> Rn;
+ let Inst{31-24} = 0b00011001;
+ let Inst{23-22} = AR;
+ let Inst{21} = 0b1;
+ let Inst{20-16} = Rt2;
+ let Inst{15} = o3;
+ let Inst{14-12} = op0;
+ let Inst{11-10} = 0b00;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Rt;
+}
+
+//---
+// 128-bit System Instructions (FEAT_SYSINSTR128)
+//---
+
+// Instruction encoding:
+//
+// 31 19|18 16|15 12|11 8|7 5|4 0
+// SYSP 1101010101001| op1| Cn| Cm|op2| Rt
+
+// Instruction syntax:
+//
+// SYSP #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>, <Xt+1>}
+
+class RtSystemI128<bit L, dag oops, dag iops, string asm, string operands, list<dag> pattern = []> :
+ RtSystemI<L, oops, iops, asm, operands, pattern> {
+ let Inst{22} = 0b1; // override BaseSystemI
+}
+
+class BaseSYSPEncoding<bit L, string asm, string operands, dag outputs, dag inputs>
+ : RtSystemI128<L, outputs, inputs, asm, operands> {
+ bits<3> op1;
+ bits<4> Cn;
+ bits<4> Cm;
+ bits<3> op2;
+ let Inst{20-19} = 0b01;
+ let Inst{18-16} = op1;
+ let Inst{15-12} = Cn;
+ let Inst{11-8} = Cm;
+ let Inst{7-5} = op2;
+}
+class SystemPXtI<bit L, string asm> :
+ BaseSYSPEncoding<L, asm, "\t$op1, $Cn, $Cm, $op2, $Rt", (outs),
+ (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XSeqPairClassOperand:$Rt)>;
+
+
//----------------------------------------------------------------------------
// Allow the size specifier tokens to be upper case, not just lower.
def : TokenAlias<".4B", ".4b">; // Add dot product
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 27bf285f9740d..427f5dc152a2d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -234,8 +234,14 @@ def HasMOPS : Predicate<"Subtarget->hasMOPS()">,
AssemblerPredicateWithAll<(all_of FeatureMOPS), "mops">;
def HasITE : Predicate<"Subtarget->hasITE()">,
AssemblerPredicateWithAll<(all_of FeatureITE), "ite">;
+def HasTHE : Predicate<"Subtarget->hasTHE()">,
+ AssemblerPredicateWithAll<(all_of FeatureTHE), "the">;
def HasRCPC3 : Predicate<"Subtarget->hasRCPC3()">,
- AssemblerPredicate<(all_of FeatureRCPC3), "rcpc3">;
+ AssemblerPredicateWithAll<(all_of FeatureRCPC3), "rcpc3">;
+def HasLSE128 : Predicate<"Subtarget->hasLSE128()">,
+ AssemblerPredicateWithAll<(all_of FeatureLSE128), "lse128">;
+def HasD128 : Predicate<"Subtarget->hasD128()">,
+ AssemblerPredicateWithAll<(all_of FeatureD128), "d128">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
@@ -8513,6 +8519,11 @@ def : Pat<(AArch64AssertZExtBool GPR32:$op),
//===----------------------------===//
// 2022 Architecture Extensions:
//===----------------------------===//
+defm RCW : ReadCheckWriteCompareAndSwap;
+
+defm RCWCLR : ReadCheckWriteOperation<0b001, "clr">;
+defm RCWSET : ReadCheckWriteOperation<0b011, "set">;
+defm RCWSWP : ReadCheckWriteOperation<0b010, "swp">;
//===----------------------------------------------------------------------===//
// General Data-Processing Instructions (FEAT_V94_DP)
@@ -8551,6 +8562,24 @@ def RPRFM:
let DecoderNamespace = "Fallback";
}
+//===----------------------------------------------------------------------===//
+// 128-bit Atomics (FEAT_LSE128)
+//===----------------------------------------------------------------------===//
+let Predicates = [HasLSE128] in {
+ def SWPP : LSE128Base<0b000, 0b00, 0b1, "swpp">;
+ def SWPPA : LSE128Base<0b000, 0b10, 0b1, "swppa">;
+ def SWPPAL : LSE128Base<0b000, 0b11, 0b1, "swppal">;
+ def SWPPL : LSE128Base<0b000, 0b01, 0b1, "swppl">;
+ def LDCLRP : LSE128Base<0b001, 0b00, 0b0, "ldclrp">;
+ def LDCLRPA : LSE128Base<0b001, 0b10, 0b0, "ldclrpa">;
+ def LDCLRPAL : LSE128Base<0b001, 0b11, 0b0, "ldclrpal">;
+ def LDCLRPL : LSE128Base<0b001, 0b01, 0b0, "ldclrpl">;
+ def LDSETP : LSE128Base<0b011, 0b00, 0b0, "ldsetp">;
+ def LDSETPA : LSE128Base<0b011, 0b10, 0b0, "ldsetpa">;
+ def LDSETPAL : LSE128Base<0b011, 0b11, 0b0, "ldsetpal">;
+ def LDSETPL : LSE128Base<0b011, 0b01, 0b0, "ldsetpl">;
+}
+
//===----------------------------------------------------------------------===//
// RCPC Instructions (FEAT_LRCPC3)
//===----------------------------------------------------------------------===//
@@ -8598,6 +8627,79 @@ let Predicates = [HasRCPC3, HasNEON] in {
def : InstAlias<"stl1\t$Vt$Q, [$Rn, #0]", (STL1 VecListOned:$Vt, VectorIndexD:$Q, GPR64sp:$Rn)>;
}
+//===----------------------------------------------------------------------===//
+// 128-bit System Instructions (FEAT_SYSINSTR128)
+//===----------------------------------------------------------------------===//
+let Predicates = [HasD128] in {
+ def SYSPxt : SystemPXtI<0, "sysp">;
+
+ def SYSPxt_XZR
+ : BaseSystemI<0, (outs),
+ (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, SyspXzrPairOperand:$xzr_pair),
+ "sysp", "\t$op1, $Cn, $Cm, $op2, $xzr_pair">,
+ Sched<[WriteSys]>
+ {
+ // Had to use a custom decoder because tablegen interprets this as having 4 fields (why?)
+ // and therefore autogenerates a decoder that builds an MC representation that has 4 fields
+ // (decodeToMCInst), but when printing we expect the MC representation to have 5 fields (one
+ // extra for the XZR) because AArch64InstPrinter::printInstruction in AArch64GenAsmWriter.inc
+ // is based off of the asm template (maybe) and therefore wants to print 5 operands.
+ // I could add a bits<5> xzr_pair. But without a way to constrain it to 0b11111 here it would
+ // overlap with the main SYSP instruction.
+ let DecoderMethod = "DecodeSyspXzrInstruction";
+ bits<3> op1;
+ bits<4> Cn;
+ bits<4> Cm;
+ bits<3> op2;
+ let Inst{22} = 0b1; // override BaseSystemI
+ let Inst{20-19} = 0b01;
+ let Inst{18-16} = op1;
+ let Inst{15-12} = Cn;
+ let Inst{11-8} = Cm;
+ let Inst{7-5} = op2;
+ let Inst{4-0} = 0b11111;
+ }
+
+ def : InstAlias<"sysp $op1, $Cn, $Cm, $op2",
+ (SYSPxt_XZR imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
+}
+
+//---
+// 128-bit System Registers (FEAT_SYSREG128)
+//---
+
+// Instruction encoding:
+//
+// 31 22|21|20|19|18 16|15 12|11 8|7 5|4 0
+// MRRS 1101010101| 1| 1|o0| op1| Cn| Cm|op2| Rt
+// MSRR 1101010101| 0| 1|o0| op1| Cn| Cm|op2| Rt
+
+// Instruction syntax:
+//
+// MRRS <Xt>, <Xt+1>, <sysreg|S<op0>_<op1>_<Cn>_<Cm>_<op2>>
+// MSRR <sysreg|S<op0>_<op1>_<Cn>_<Cm>_<op2>>, <Xt>, <Xt+1>
+//
+// ...where t is even (X0, X2, etc).
+
+let Predicates = [HasD128] in {
+ def MRRS : RtSystemI128<1,
+ (outs MrrsMssrPairClassOperand:$Rt), (ins mrs_sysreg_op:$systemreg),
+ "mrrs", "\t$Rt, $systemreg">
+ {
+ bits<16> systemreg;
+ let Inst{20-5} = systemreg;
+ }
+
+ def MSRR : RtSystemI128<0,
+ (outs), (ins msr_sysreg_op:$systemreg, MrrsMssrPairClassOperand:$Rt),
+ "msrr", "\t$systemreg, $Rt">
+ {
+ bits<16> systemreg;
+ let Inst{20-5} = systemreg;
+ }
+}
+
+
include "AArch64InstrAtomics.td"
include "AArch64SVEInstrInfo.td"
include "AArch64SMEInstrInfo.td"
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index ea6e25d8d3f62..fa135eb0c7409 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -720,6 +720,21 @@ def XSeqPairClassOperand :
RegisterOperand<XSeqPairsClass, "printGPRSeqPairsClassOperand<64>"> {
let ParserMatchClass = XSeqPairsAsmOperandClass;
}
+// Reuse the parsing and register numbers from XSeqPairs, but encoding is
diff erent.
+def MrrsMssrPairClassOperand :
+ RegisterOperand<XSeqPairsClass, "printGPRSeqPairsClassOperand<64>"> {
+ let ParserMatchClass = XSeqPairsAsmOperandClass;
+}
+def SyspXzrPairOperandMatcherClass : AsmOperandClass {
+ let Name = "SyspXzrPair";
+ let RenderMethod = "addSyspXzrPairOperand";
+ let ParserMethod = "tryParseSyspXzrPair";
+}
+def SyspXzrPairOperand :
+ RegisterOperand<GPR64, "printSyspXzrPair"> { // needed to allow alias with XZR operand
+ let ParserMatchClass = SyspXzrPairOperandMatcherClass;
+}
+
//===----- END: v8.1a atomic CASP register operands -----------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td b/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td
index a3a038f869fbb..d5788795c7a13 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td
@@ -1259,7 +1259,8 @@ def : InstRW<[FalkorWr_1SD_1ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt],
(instrs STNPWi, STNPXi)>;
def : InstRW<[FalkorWr_2LD_1Z_3cyc], (instrs ERET)>;
-def : InstRW<[FalkorWr_1ST_1SD_1LD_3cyc], (instregex "^LDC.*$")>;
+
+def : InstRW<[FalkorWr_1ST_1SD_1LD_3cyc], (instregex "^LDCLR(A|AL|L)?(B|H)?$")>;
def : InstRW<[FalkorWr_1ST_1SD_1LD_0cyc, ReadDefault, FalkorReadIncSt],
(instregex "^STLR(B|H|W|X)$")>;
def : InstRW<[FalkorWr_1ST_1SD_1LD_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt],
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 1639fca4a465f..c49c6f3a41fe0 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -1727,6 +1727,61 @@ let Requires = [{ {AArch64::FeatureMPAM, AArch64::FeatureSME} }] in {
def : RWSysReg<"MPAMSM_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b011>;
} // HasMPAM, HasSME
+// v8.9a/v9.4a Memory Attribute Index Enhancement (FEAT_AIE)
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"AMAIR2_EL1", 0b11, 0b000, 0b1010, 0b0011, 0b001>;
+def : RWSysReg<"AMAIR2_EL12", 0b11, 0b101, 0b1010, 0b0011, 0b001>;
+def : RWSysReg<"AMAIR2_EL2", 0b11, 0b100, 0b1010, 0b0011, 0b001>;
+def : RWSysReg<"AMAIR2_EL3", 0b11, 0b110, 0b1010, 0b0011, 0b001>;
+def : RWSysReg<"MAIR2_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b001>;
+def : RWSysReg<"MAIR2_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b001>;
+def : RWSysReg<"MAIR2_EL2", 0b11, 0b100, 0b1010, 0b0001, 0b001>;
+def : RWSysReg<"MAIR2_EL3", 0b11, 0b110, 0b1010, 0b0001, 0b001>;
+
+// v8.9a/9.4a Stage 1 Permission Indirection Extension (FEAT_S1PIE)
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"PIRE0_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b010>;
+def : RWSysReg<"PIRE0_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b010>;
+def : RWSysReg<"PIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b011>;
+def : RWSysReg<"PIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b011>;
+def : RWSysReg<"PIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b011>;
+def : RWSysReg<"PIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b011>;
+
+// v8.9a/v9.4a Stage 2 Permission Indirection Extension (FEAT_S2PIE)
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"S2PIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b101>;
+
+// v8.9a/v9.4a Stage 1 Permission Overlay Extension (FEAT_S1POE)
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"POR_EL0", 0b11, 0b011, 0b1010, 0b0010, 0b100>;
+def : RWSysReg<"POR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b100>;
+def : RWSysReg<"POR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b100>;
+def : RWSysReg<"POR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b100>;
+def : RWSysReg<"POR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b100>;
+
+// v8.9a/v9.4a Stage 2 Permission Overlay Extension (FEAT_S2POE)
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"S2POR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b101>;
+
+// v8.9a/v9.4a Extension to System Control Registers (FEAT_SCTLR2)
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"SCTLR2_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b011>;
+def : RWSysReg<"SCTLR2_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b011>;
+def : RWSysReg<"SCTLR2_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b011>;
+
+// v8.9a/v9.4a Extension to Translation Control Registers (FEAT_TCR2)
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"TCR2_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b011>;
+def : RWSysReg<"TCR2_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b011>;
+def : RWSysReg<"TCR2_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b011>;
+
+// v8.9a/9.4a Translation Hardening Extension (FEAT_THE)
+// Op0 Op1 CRn CRm Op2
+let Requires = [{ {AArch64::FeatureTHE} }] in {
+def : RWSysReg<"RCWMASK_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b110>;
+def : RWSysReg<"RCWSMASK_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b011>;
+}
+
// v8.9a/9.4a new Debug feature (FEAT_DEBUGv8p9)
// Op0 Op1 CRn CRm Op2
def : RWSysReg<"MDSELR_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b010>;
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index ca4717f0c3cf0..8556bd7c6d875 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -159,6 +159,7 @@ class AArch64AsmParser : public MCTargetAsmParser {
SMLoc getLoc() const { return getParser().getTok().getLoc(); }
bool parseSysAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands);
+ bool parseSyspAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands);
void createSysAlias(uint16_t Encoding, OperandVector &Operands, SMLoc S);
AArch64CC::CondCode parseCondCodeString(StringRef Cond,
std::string &Suggestion);
@@ -265,6 +266,7 @@ class AArch64AsmParser : public MCTargetAsmParser {
bool tryParseNeonVectorRegister(OperandVector &Operands);
OperandMatchResultTy tryParseVectorIndex(OperandVector &Operands);
OperandMatchResultTy tryParseGPRSeqPair(OperandVector &Operands);
+ OperandMatchResultTy tryParseSyspXzrPair(OperandVector &Operands);
template <bool ParseShiftExtend,
RegConstraintEqualityTy EqTy = RegConstraintEqualityTy::EqualsReg>
OperandMatchResultTy tryParseGPROperand(OperandVector &Operands);
@@ -1349,6 +1351,10 @@ class AArch64Operand : public MCParsedAsmOperand {
Reg.RegNum);
}
+ bool isSyspXzrPair() const {
+ return isGPR64<AArch64::GPR64RegClassID>() && Reg.RegNum == AArch64::XZR;
+ }
+
template<int64_t Angle, int64_t Remainder>
DiagnosticPredicate isComplexRotation() const {
if (!isImm()) return DiagnosticPredicateTy::NoMatch;
@@ -2062,6 +2068,21 @@ class AArch64Operand : public MCParsedAsmOperand {
Inst.addOperand(MCOperand::createImm(Imm));
}
+ void addSyspXzrPairOperand(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+
+ if (!isScalarReg())
+ return;
+
+ const MCRegisterInfo *RI = Ctx.getRegisterInfo();
+ uint32_t Reg = RI->getRegClass(AArch64::GPR64RegClassID)
+ .getRegister(RI->getEncodingValue(getReg()));
+ if (Reg != AArch64::XZR)
+ llvm_unreachable("wrong register");
+
+ Inst.addOperand(MCOperand::createReg(AArch64::XZR));
+ }
+
void addExtendOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
AArch64_AM::ShiftExtendType ET = getShiftExtendType();
@@ -3086,6 +3107,44 @@ AArch64AsmParser::tryParsePSBHint(OperandVector &Operands) {
return MatchOperand_Success;
}
+OperandMatchResultTy
+AArch64AsmParser::tryParseSyspXzrPair(OperandVector &Operands) {
+ SMLoc StartLoc = getLoc();
+
+ unsigned RegNum;
+
+ // The case where xzr, xzr is not present is handled by an InstAlias.
+
+ auto RegTok = getTok(); // in case we need to backtrack
+ if (tryParseScalarRegister(RegNum) != MatchOperand_Success)
+ return MatchOperand_NoMatch;
+
+ if (RegNum != AArch64::XZR) {
+ getLexer().UnLex(RegTok);
+ return MatchOperand_NoMatch;
+ }
+
+ if (parseComma())
+ return MatchOperand_ParseFail;
+
+ if (tryParseScalarRegister(RegNum) != MatchOperand_Success) {
+ TokError("expected register operand");
+ return MatchOperand_ParseFail;
+ }
+
+ if (RegNum != AArch64::XZR) {
+ TokError("xzr must be followed by xzr");
+ return MatchOperand_ParseFail;
+ }
+
+ // We need to push something, since we claim this is an operand in .td.
+ // See also AArch64AsmParser::parseKeywordOperand.
+ Operands.push_back(AArch64Operand::CreateReg(
+ RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext()));
+
+ return MatchOperand_Success;
+}
+
/// tryParseBTIHint - Try to parse a BTI operand, mapped to Hint command
OperandMatchResultTy
AArch64AsmParser::tryParseBTIHint(OperandVector &Operands) {
@@ -3611,6 +3670,9 @@ static const struct Extension {
{"hbc", {AArch64::FeatureHBC}},
{"mops", {AArch64::FeatureMOPS}},
{"mec", {AArch64::FeatureMEC}},
+ {"the", {AArch64::FeatureTHE}},
+ {"d128", {AArch64::FeatureD128}},
+ {"lse128", {AArch64::FeatureLSE128}},
// FIXME: Unsupported extensions
{"lor", {}},
{"rdma", {}},
@@ -3777,6 +3839,65 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
return false;
}
+/// parseSyspAlias - The TLBIP instructions are simple aliases for
+/// the SYSP instruction. Parse them specially so that we create a SYSP MCInst.
+bool AArch64AsmParser::parseSyspAlias(StringRef Name, SMLoc NameLoc,
+ OperandVector &Operands) {
+ if (Name.contains('.'))
+ return TokError("invalid operand");
+
+ Mnemonic = Name;
+ Operands.push_back(
+ AArch64Operand::CreateToken("sysp", NameLoc, getContext()));
+
+ const AsmToken &Tok = getTok();
+ StringRef Op = Tok.getString();
+ SMLoc S = Tok.getLoc();
+
+ if (Mnemonic == "tlbip") {
+ bool HasnXSQualifier = Op.endswith_insensitive("nXS");
+ if (HasnXSQualifier) {
+ Op = Op.drop_back(3);
+ }
+ const AArch64TLBI::TLBI *TLBIorig = AArch64TLBI::lookupTLBIByName(Op);
+ if (!TLBIorig)
+ return TokError("invalid operand for TLBIP instruction");
+ const AArch64TLBI::TLBI TLBI(
+ TLBIorig->Name, TLBIorig->Encoding | (HasnXSQualifier ? (1 << 7) : 0),
+ TLBIorig->NeedsReg,
+ HasnXSQualifier
+ ? TLBIorig->FeaturesRequired | FeatureBitset({AArch64::FeatureXS})
+ : TLBIorig->FeaturesRequired);
+ if (!TLBI.haveFeatures(getSTI().getFeatureBits())) {
+ std::string Name =
+ std::string(TLBI.Name) + (HasnXSQualifier ? "nXS" : "");
+ std::string Str("TLBIP " + Name + " requires: ");
+ setRequiredFeatureString(TLBI.getRequiredFeatures(), Str);
+ return TokError(Str);
+ }
+ createSysAlias(TLBI.Encoding, Operands, S);
+ }
+
+ Lex(); // Eat operand.
+
+ if (parseComma())
+ return true;
+
+ if (Tok.isNot(AsmToken::Identifier))
+ return TokError("expected register identifier");
+ auto Result = tryParseSyspXzrPair(Operands);
+ if (Result == MatchOperand_NoMatch)
+ Result = tryParseGPRSeqPair(Operands);
+ if (Result != MatchOperand_Success)
+ return TokError("specified " + Mnemonic +
+ " op requires a pair of registers");
+
+ if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list"))
+ return true;
+
+ return false;
+}
+
OperandMatchResultTy
AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
@@ -4962,6 +5083,10 @@ bool AArch64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
Head == "cfp" || Head == "dvp" || Head == "cpp")
return parseSysAlias(Head, NameLoc, Operands);
+ // TLBIP instructions are aliases for the SYSP instruction.
+ if (Head == "tlbip")
+ return parseSyspAlias(Head, NameLoc, Operands);
+
Operands.push_back(AArch64Operand::CreateToken(Head, NameLoc, getContext()));
Mnemonic = Head;
@@ -7588,8 +7713,11 @@ AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
unsigned FirstReg;
OperandMatchResultTy Res = tryParseScalarRegister(FirstReg);
- if (Res != MatchOperand_Success)
+ if (Res != MatchOperand_Success) {
+ Error(S, "expected first even register of a "
+ "consecutive same-size even/odd register pair");
return MatchOperand_ParseFail;
+ }
const MCRegisterClass &WRegClass =
AArch64MCRegisterClasses[AArch64::GPR32RegClassID];
@@ -7623,13 +7751,16 @@ AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
SMLoc E = getLoc();
unsigned SecondReg;
Res = tryParseScalarRegister(SecondReg);
- if (Res != MatchOperand_Success)
+ if (Res != MatchOperand_Success) {
+ Error(E, "expected second odd register of a "
+ "consecutive same-size even/odd register pair");
return MatchOperand_ParseFail;
+ }
if (RI->getEncodingValue(SecondReg) != FirstEncoding + 1 ||
(isXReg && !XRegClass.contains(SecondReg)) ||
(isWReg && !WRegClass.contains(SecondReg))) {
- Error(E,"expected second odd register of a "
+ Error(E, "expected second odd register of a "
"consecutive same-size even/odd register pair");
return MatchOperand_ParseFail;
}
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index ff644517b4ec5..511e37eea25ad 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -262,6 +262,9 @@ DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
static DecodeStatus
DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
const MCDisassembler *Decoder);
+static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
+ uint64_t Addr,
+ const MCDisassembler *Decoder);
static DecodeStatus
DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
const MCDisassembler *Decoder);
@@ -1892,6 +1895,26 @@ DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
RegNo, Addr, Decoder);
}
+static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
+ uint64_t Addr,
+ const MCDisassembler *Decoder) {
+ unsigned op1 = fieldFromInstruction(insn, 16, 3);
+ unsigned CRn = fieldFromInstruction(insn, 12, 4);
+ unsigned CRm = fieldFromInstruction(insn, 8, 4);
+ unsigned op2 = fieldFromInstruction(insn, 5, 3);
+ unsigned Rt = fieldFromInstruction(insn, 0, 5);
+ if (Rt != 0b11111)
+ return Fail;
+
+ Inst.addOperand(MCOperand::createImm(op1));
+ Inst.addOperand(MCOperand::createImm(CRn));
+ Inst.addOperand(MCOperand::createImm(CRm));
+ Inst.addOperand(MCOperand::createImm(op2));
+ DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
+
+ return Success;
+}
+
static DecodeStatus
DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
const MCDisassembler *Decoder) {
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
index 1f8c85914716a..8525308e6b2a7 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -81,6 +81,12 @@ void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
return;
}
+ if (Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR)
+ if (printSyspAlias(MI, STI, O)) {
+ printAnnotation(O, Annot);
+ return;
+ }
+
// RPRFM overlaps PRFM (reg), so try to print it as RPRFM here.
if ((Opcode == AArch64::PRFMroX) || (Opcode == AArch64::PRFMroW)) {
if (printRangePrefetchAlias(MI, STI, O, Annot))
@@ -979,6 +985,66 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
return true;
}
+bool AArch64InstPrinter::printSyspAlias(const MCInst *MI,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+#ifndef NDEBUG
+ unsigned Opcode = MI->getOpcode();
+ assert((Opcode == AArch64::SYSPxt || Opcode == AArch64::SYSPxt_XZR) &&
+ "Invalid opcode for SYSP alias!");
+#endif
+
+ const MCOperand &Op1 = MI->getOperand(0);
+ const MCOperand &Cn = MI->getOperand(1);
+ const MCOperand &Cm = MI->getOperand(2);
+ const MCOperand &Op2 = MI->getOperand(3);
+
+ unsigned Op1Val = Op1.getImm();
+ unsigned CnVal = Cn.getImm();
+ unsigned CmVal = Cm.getImm();
+ unsigned Op2Val = Op2.getImm();
+
+ uint16_t Encoding = Op2Val;
+ Encoding |= CmVal << 3;
+ Encoding |= CnVal << 7;
+ Encoding |= Op1Val << 11;
+
+ std::string Ins;
+ std::string Name;
+
+ if (CnVal == 8 || CnVal == 9) {
+ // TLBIP aliases
+
+ if (CnVal == 9) {
+ if (!STI.hasFeature(AArch64::FeatureXS))
+ return false;
+ Encoding &= ~(1 << 7);
+ }
+
+ const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
+ if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
+ return false;
+
+ Ins = "tlbip\t";
+ Name = std::string(TLBI->Name);
+ if (CnVal == 9)
+ Name += "nXS";
+ } else
+ return false;
+
+ std::string Str = Ins + Name;
+ std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower);
+
+ O << '\t' << Str;
+ O << ", ";
+ if (MI->getOperand(4).getReg() == AArch64::XZR)
+ printSyspXzrPair(MI, 4, STI, O);
+ else
+ printGPRSeqPairsClassOperand<64>(MI, 4, STI, O);
+
+ return true;
+}
+
template <int EltSize>
void AArch64InstPrinter::printMatrix(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
@@ -2013,3 +2079,12 @@ void AArch64InstPrinter::printGPR64x8(const MCInst *MI, unsigned OpNum,
unsigned Reg = MI->getOperand(OpNum).getReg();
printRegName(O, MRI.getSubReg(Reg, AArch64::x8sub_0));
}
+
+void AArch64InstPrinter::printSyspXzrPair(const MCInst *MI, unsigned OpNum,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ unsigned Reg = MI->getOperand(OpNum).getReg();
+ assert(Reg == AArch64::XZR &&
+ "MC representation of SyspXzrPair should be XZR");
+ O << getRegisterName(Reg) << ", " << getRegisterName(Reg);
+}
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
index 3c3ee5f4fb8d4..37d0225b45cfe 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
@@ -53,6 +53,8 @@ class AArch64InstPrinter : public MCInstPrinter {
protected:
bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O);
+ bool printSyspAlias(const MCInst *MI, const MCSubtargetInfo &STI,
+ raw_ostream &O);
bool printRangePrefetchAlias(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O, StringRef Annot);
// Operand printers
@@ -227,6 +229,8 @@ class AArch64InstPrinter : public MCInstPrinter {
const MCSubtargetInfo &STI, raw_ostream &O);
void printGPR64x8(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
+ void printSyspXzrPair(const MCInst *MI, unsigned OpNum,
+ const MCSubtargetInfo &STI, raw_ostream &O);
template <int Width>
void printZPRasFPR(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O);
diff --git a/llvm/test/MC/AArch64/arm64-system-encoding.s b/llvm/test/MC/AArch64/arm64-system-encoding.s
index 2e26d18bbf511..744d35f4edbfe 100644
--- a/llvm/test/MC/AArch64/arm64-system-encoding.s
+++ b/llvm/test/MC/AArch64/arm64-system-encoding.s
@@ -134,6 +134,33 @@ foo:
msr VTCR_EL2, x3
msr VTTBR_EL2, x3
msr SPSel, x3
+ msr AMAIR2_EL1, x3
+ msr AMAIR2_EL12, x3
+ msr AMAIR2_EL2, x3
+ msr AMAIR2_EL3, x3
+ msr MAIR2_EL1, x3
+ msr MAIR2_EL12, x3
+ msr MAIR2_EL2, x3
+ msr MAIR2_EL3, x3
+ msr PIRE0_EL1, x3
+ msr PIRE0_EL2, x3
+ msr PIR_EL1, x3
+ msr PIR_EL12, x3
+ msr PIR_EL2, x3
+ msr PIR_EL3, x3
+ msr S2PIR_EL2, x3
+ msr POR_EL0, x3
+ msr POR_EL1, x3
+ msr POR_EL12, x3
+ msr POR_EL2, x3
+ msr POR_EL3, x3
+ msr S2POR_EL1, x3
+ msr SCTLR2_EL1, x3
+ msr SCTLR2_EL12, x3
+ msr SCTLR2_EL2, x3
+ msr TCR2_EL1, x3
+ msr TCR2_EL12, x3
+ msr TCR2_EL2, x3
msr S3_2_C11_C6_4, x1
msr S0_0_C0_C0_0, x0
msr S1_2_C3_C4_5, x2
@@ -213,6 +240,33 @@ foo:
; CHECK: msr VTCR_EL2, x3 ; encoding: [0x43,0x21,0x1c,0xd5]
; CHECK: msr VTTBR_EL2, x3 ; encoding: [0x03,0x21,0x1c,0xd5]
; CHECK: msr SPSel, x3 ; encoding: [0x03,0x42,0x18,0xd5]
+; CHECK: msr AMAIR2_EL1, x3 ; encoding: [0x23,0xa3,0x18,0xd5]
+; CHECK: msr AMAIR2_EL12, x3 ; encoding: [0x23,0xa3,0x1d,0xd5]
+; CHECK: msr AMAIR2_EL2, x3 ; encoding: [0x23,0xa3,0x1c,0xd5]
+; CHECK: msr AMAIR2_EL3, x3 ; encoding: [0x23,0xa3,0x1e,0xd5]
+; CHECK: msr MAIR2_EL1, x3 ; encoding: [0x23,0xa2,0x18,0xd5]
+; CHECK: msr MAIR2_EL12, x3 ; encoding: [0x23,0xa2,0x1d,0xd5]
+; CHECK: msr MAIR2_EL2, x3 ; encoding: [0x23,0xa1,0x1c,0xd5]
+; CHECK: msr MAIR2_EL3, x3 ; encoding: [0x23,0xa1,0x1e,0xd5]
+; CHECK: msr PIRE0_EL1, x3 ; encoding: [0x43,0xa2,0x18,0xd5]
+; CHECK: msr PIRE0_EL2, x3 ; encoding: [0x43,0xa2,0x1c,0xd5]
+; CHECK: msr PIR_EL1, x3 ; encoding: [0x63,0xa2,0x18,0xd5]
+; CHECK: msr PIR_EL12, x3 ; encoding: [0x63,0xa2,0x1d,0xd5]
+; CHECK: msr PIR_EL2, x3 ; encoding: [0x63,0xa2,0x1c,0xd5]
+; CHECK: msr PIR_EL3, x3 ; encoding: [0x63,0xa2,0x1e,0xd5]
+; CHECK: msr S2PIR_EL2, x3 ; encoding: [0xa3,0xa2,0x1c,0xd5]
+; CHECK: msr POR_EL0, x3 ; encoding: [0x83,0xa2,0x1b,0xd5]
+; CHECK: msr POR_EL1, x3 ; encoding: [0x83,0xa2,0x18,0xd5]
+; CHECK: msr POR_EL12, x3 ; encoding: [0x83,0xa2,0x1d,0xd5]
+; CHECK: msr POR_EL2, x3 ; encoding: [0x83,0xa2,0x1c,0xd5]
+; CHECK: msr POR_EL3, x3 ; encoding: [0x83,0xa2,0x1e,0xd5]
+; CHECK: msr S2POR_EL1, x3 ; encoding: [0xa3,0xa2,0x18,0xd5]
+; CHECK: msr SCTLR2_EL1, x3 ; encoding: [0x63,0x10,0x18,0xd5]
+; CHECK: msr SCTLR2_EL12, x3 ; encoding: [0x63,0x10,0x1d,0xd5]
+; CHECK: msr SCTLR2_EL2, x3 ; encoding: [0x63,0x10,0x1c,0xd5]
+; CHECK: msr TCR2_EL1, x3 ; encoding: [0x63,0x20,0x18,0xd5]
+; CHECK: msr TCR2_EL12, x3 ; encoding: [0x63,0x20,0x1d,0xd5]
+; CHECK: msr TCR2_EL2, x3 ; encoding: [0x63,0x20,0x1c,0xd5]
; CHECK: msr S3_2_C11_C6_4, x1 ; encoding: [0x81,0xb6,0x1a,0xd5]
; CHECK: msr S0_0_C0_C0_0, x0 ; encoding: [0x00,0x00,0x00,0xd5]
; CHECK: msr S1_2_C3_C4_5, x2 ; encoding: [0xa2,0x34,0x0a,0xd5]
@@ -404,6 +458,33 @@ foo:
mrs x3, DBGCLAIMSET_EL1
mrs x3, DBGCLAIMCLR_EL1
mrs x3, DBGAUTHSTATUS_EL1
+ mrs x3, AMAIR2_EL1
+ mrs x3, AMAIR2_EL12
+ mrs x3, AMAIR2_EL2
+ mrs x3, AMAIR2_EL3
+ mrs x3, MAIR2_EL1
+ mrs x3, MAIR2_EL12
+ mrs x3, MAIR2_EL2
+ mrs x3, MAIR2_EL3
+ mrs x3, PIRE0_EL1
+ mrs x3, PIRE0_EL2
+ mrs x3, PIR_EL1
+ mrs x3, PIR_EL12
+ mrs x3, PIR_EL2
+ mrs x3, PIR_EL3
+ mrs x3, S2PIR_EL2
+ mrs x3, POR_EL0
+ mrs x3, POR_EL1
+ mrs x3, POR_EL12
+ mrs x3, POR_EL2
+ mrs x3, POR_EL3
+ mrs x3, S2POR_EL1
+ mrs x3, SCTLR2_EL1
+ mrs x3, SCTLR2_EL12
+ mrs x3, SCTLR2_EL2
+ mrs x3, TCR2_EL1
+ mrs x3, TCR2_EL12
+ mrs x3, TCR2_EL2
mrs x1, S3_2_C15_C6_4
mrs x3, s3_3_c11_c1_4
mrs x3, S3_3_c11_c1_4
@@ -590,6 +671,33 @@ foo:
; CHECK: mrs x3, DBGCLAIMSET_EL1 ; encoding: [0xc3,0x78,0x30,0xd5]
; CHECK: mrs x3, DBGCLAIMCLR_EL1 ; encoding: [0xc3,0x79,0x30,0xd5]
; CHECK: mrs x3, DBGAUTHSTATUS_EL1 ; encoding: [0xc3,0x7e,0x30,0xd5]
+; CHECK: mrs x3, AMAIR2_EL1 ; encoding: [0x23,0xa3,0x38,0xd5]
+; CHECK: mrs x3, AMAIR2_EL12 ; encoding: [0x23,0xa3,0x3d,0xd5]
+; CHECK: mrs x3, AMAIR2_EL2 ; encoding: [0x23,0xa3,0x3c,0xd5]
+; CHECK: mrs x3, AMAIR2_EL3 ; encoding: [0x23,0xa3,0x3e,0xd5]
+; CHECK: mrs x3, MAIR2_EL1 ; encoding: [0x23,0xa2,0x38,0xd5]
+; CHECK: mrs x3, MAIR2_EL12 ; encoding: [0x23,0xa2,0x3d,0xd5]
+; CHECK: mrs x3, MAIR2_EL2 ; encoding: [0x23,0xa1,0x3c,0xd5]
+; CHECK: mrs x3, MAIR2_EL3 ; encoding: [0x23,0xa1,0x3e,0xd5]
+; CHECK: mrs x3, PIRE0_EL1 ; encoding: [0x43,0xa2,0x38,0xd5]
+; CHECK: mrs x3, PIRE0_EL2 ; encoding: [0x43,0xa2,0x3c,0xd5]
+; CHECK: mrs x3, PIR_EL1 ; encoding: [0x63,0xa2,0x38,0xd5]
+; CHECK: mrs x3, PIR_EL12 ; encoding: [0x63,0xa2,0x3d,0xd5]
+; CHECK: mrs x3, PIR_EL2 ; encoding: [0x63,0xa2,0x3c,0xd5]
+; CHECK: mrs x3, PIR_EL3 ; encoding: [0x63,0xa2,0x3e,0xd5]
+; CHECK: mrs x3, S2PIR_EL2 ; encoding: [0xa3,0xa2,0x3c,0xd5]
+; CHECK: mrs x3, POR_EL0 ; encoding: [0x83,0xa2,0x3b,0xd5]
+; CHECK: mrs x3, POR_EL1 ; encoding: [0x83,0xa2,0x38,0xd5]
+; CHECK: mrs x3, POR_EL12 ; encoding: [0x83,0xa2,0x3d,0xd5]
+; CHECK: mrs x3, POR_EL2 ; encoding: [0x83,0xa2,0x3c,0xd5]
+; CHECK: mrs x3, POR_EL3 ; encoding: [0x83,0xa2,0x3e,0xd5]
+; CHECK: mrs x3, S2POR_EL1 ; encoding: [0xa3,0xa2,0x38,0xd5]
+; CHECK: mrs x3, SCTLR2_EL1 ; encoding: [0x63,0x10,0x38,0xd5]
+; CHECK: mrs x3, SCTLR2_EL12 ; encoding: [0x63,0x10,0x3d,0xd5]
+; CHECK: mrs x3, SCTLR2_EL2 ; encoding: [0x63,0x10,0x3c,0xd5]
+; CHECK: mrs x3, TCR2_EL1 ; encoding: [0x63,0x20,0x38,0xd5]
+; CHECK: mrs x3, TCR2_EL12 ; encoding: [0x63,0x20,0x3d,0xd5]
+; CHECK: mrs x3, TCR2_EL2 ; encoding: [0x63,0x20,0x3c,0xd5]
; CHECK: mrs x1, S3_2_C15_C6_4 ; encoding: [0x81,0xf6,0x3a,0xd5]
; CHECK: mrs x3, S3_3_C11_C1_4 ; encoding: [0x83,0xb1,0x3b,0xd5]
; CHECK: mrs x3, S3_3_C11_C1_4 ; encoding: [0x83,0xb1,0x3b,0xd5]
diff --git a/llvm/test/MC/AArch64/armv8.9a-the.s b/llvm/test/MC/AArch64/armv8.9a-the.s
new file mode 100644
index 0000000000000..33e1b5d27fa76
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv8.9a-the.s
@@ -0,0 +1,592 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+the -mattr=+d128 < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a -mattr=+the -mattr=+d128 < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a -mattr=+the -mattr=+d128 < %s | FileCheck %s
+
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-THE %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.9a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-THE %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v9.4a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-THE %s
+
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+the < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-D128 %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.9a -mattr=+the < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-D128 %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v9.4a -mattr=+the < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-D128 %s
+
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+the -mattr=+d128 < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ZXR %s
+
+ mrs x3, RCWMASK_EL1
+// CHECK: mrs x3, RCWMASK_EL1 // encoding: [0xc3,0xd0,0x38,0xd5]
+// ERROR-NO-THE: [[@LINE-2]]:21: error: expected readable system register
+ msr RCWMASK_EL1, x1
+// CHECK: msr RCWMASK_EL1, x1 // encoding: [0xc1,0xd0,0x18,0xd5]
+// ERROR-NO-THE: [[@LINE-2]]:17: error: expected writable system register or pstate
+ mrs x3, RCWSMASK_EL1
+// CHECK: mrs x3, RCWSMASK_EL1 // encoding: [0x63,0xd0,0x38,0xd5]
+// ERROR-NO-THE: [[@LINE-2]]:21: error: expected readable system register
+ msr RCWSMASK_EL1, x1
+// CHECK: msr RCWSMASK_EL1, x1 // encoding: [0x61,0xd0,0x18,0xd5]
+// ERROR-NO-THE: [[@LINE-2]]:17: error: expected writable system register or pstate
+
+ rcwcas x0, x1, [x4]
+// CHECK: rcwcas x0, x1, [x4] // encoding: [0x81,0x08,0x20,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwcasa x0, x1, [x4]
+// CHECK: rcwcasa x0, x1, [x4] // encoding: [0x81,0x08,0xa0,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwcasal x0, x1, [x4]
+// CHECK: rcwcasal x0, x1, [x4] // encoding: [0x81,0x08,0xe0,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwcasl x0, x1, [x4]
+// CHECK: rcwcasl x0, x1, [x4] // encoding: [0x81,0x08,0x60,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwcas x3, x5, [sp]
+// CHECK: rcwcas x3, x5, [sp] // encoding: [0xe5,0x0b,0x23,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwcasa x3, x5, [sp]
+// CHECK: rcwcasa x3, x5, [sp] // encoding: [0xe5,0x0b,0xa3,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwcasal x3, x5, [sp]
+// CHECK: rcwcasal x3, x5, [sp] // encoding: [0xe5,0x0b,0xe3,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwcasl x3, x5, [sp]
+// CHECK: rcwcasl x3, x5, [sp] // encoding: [0xe5,0x0b,0x63,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+
+ rcwscas x0, x1, [x4]
+// CHECK: rcwscas x0, x1, [x4] // encoding: [0x81,0x08,0x20,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwscasa x0, x1, [x4]
+// CHECK: rcwscasa x0, x1, [x4] // encoding: [0x81,0x08,0xa0,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwscasal x0, x1, [x4]
+// CHECK: rcwscasal x0, x1, [x4] // encoding: [0x81,0x08,0xe0,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwscasl x0, x1, [x4]
+// CHECK: rcwscasl x0, x1, [x4] // encoding: [0x81,0x08,0x60,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwscas x3, x5, [sp]
+// CHECK: rcwscas x3, x5, [sp] // encoding: [0xe5,0x0b,0x23,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwscasa x3, x5, [sp]
+// CHECK: rcwscasa x3, x5, [sp] // encoding: [0xe5,0x0b,0xa3,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwscasal x3, x5, [sp]
+// CHECK: rcwscasal x3, x5, [sp] // encoding: [0xe5,0x0b,0xe3,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwscasl x3, x5, [sp]
+// CHECK: rcwscasl x3, x5, [sp] // encoding: [0xe5,0x0b,0x63,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+
+ rcwcasp x0, x1, x6, x7, [x4]
+// CHECK: rcwcasp x0, x1, x6, x7, [x4] // encoding: [0x86,0x0c,0x20,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwcaspa x0, x1, x6, x7, [x4]
+// CHECK: rcwcaspa x0, x1, x6, x7, [x4] // encoding: [0x86,0x0c,0xa0,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwcaspal x0, x1, x6, x7, [x4]
+// CHECK: rcwcaspal x0, x1, x6, x7, [x4] // encoding: [0x86,0x0c,0xe0,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwcaspl x0, x1, x6, x7, [x4]
+// CHECK: rcwcaspl x0, x1, x6, x7, [x4] // encoding: [0x86,0x0c,0x60,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwcasp x4, x5, x6, x7, [sp]
+// CHECK: rcwcasp x4, x5, x6, x7, [sp] // encoding: [0xe6,0x0f,0x24,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwcaspa x4, x5, x6, x7, [sp]
+// CHECK: rcwcaspa x4, x5, x6, x7, [sp] // encoding: [0xe6,0x0f,0xa4,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwcaspal x4, x5, x6, x7, [sp]
+// CHECK: rcwcaspal x4, x5, x6, x7, [sp] // encoding: [0xe6,0x0f,0xe4,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwcaspl x4, x5, x6, x7, [sp]
+// CHECK: rcwcaspl x4, x5, x6, x7, [sp] // encoding: [0xe6,0x0f,0x64,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+
+ rcwscasp x0, x1, x6, x7, [x4]
+// CHECK: rcwscasp x0, x1, x6, x7, [x4] // encoding: [0x86,0x0c,0x20,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwscaspa x0, x1, x6, x7, [x4]
+// CHECK: rcwscaspa x0, x1, x6, x7, [x4] // encoding: [0x86,0x0c,0xa0,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwscaspal x0, x1, x6, x7, [x4]
+// CHECK: rcwscaspal x0, x1, x6, x7, [x4] // encoding: [0x86,0x0c,0xe0,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwscaspl x0, x1, x6, x7, [x4]
+// CHECK: rcwscaspl x0, x1, x6, x7, [x4] // encoding: [0x86,0x0c,0x60,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwscasp x4, x5, x6, x7, [sp]
+// CHECK: rcwscasp x4, x5, x6, x7, [sp] // encoding: [0xe6,0x0f,0x24,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwscaspa x4, x5, x6, x7, [sp]
+// CHECK: rcwscaspa x4, x5, x6, x7, [sp] // encoding: [0xe6,0x0f,0xa4,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwscaspal x4, x5, x6, x7, [sp]
+// CHECK: rcwscaspal x4, x5, x6, x7, [sp] // encoding: [0xe6,0x0f,0xe4,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwscaspl x4, x5, x6, x7, [sp]
+// CHECK: rcwscaspl x4, x5, x6, x7, [sp] // encoding: [0xe6,0x0f,0x64,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+
+ rcwclr x0, x1, [x4]
+// CHECK: rcwclr x0, x1, [x4] // encoding: [0x81,0x90,0x20,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwclra x0, x1, [x4]
+// CHECK: rcwclra x0, x1, [x4] // encoding: [0x81,0x90,0xa0,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwclral x0, x1, [x4]
+// CHECK: rcwclral x0, x1, [x4] // encoding: [0x81,0x90,0xe0,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwclrl x0, x1, [x4]
+// CHECK: rcwclrl x0, x1, [x4] // encoding: [0x81,0x90,0x60,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwclr x3, x5, [sp]
+// CHECK: rcwclr x3, x5, [sp] // encoding: [0xe5,0x93,0x23,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwclra x3, x5, [sp]
+// CHECK: rcwclra x3, x5, [sp] // encoding: [0xe5,0x93,0xa3,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwclral x3, x5, [sp]
+// CHECK: rcwclral x3, x5, [sp] // encoding: [0xe5,0x93,0xe3,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwclrl x3, x5, [sp]
+// CHECK: rcwclrl x3, x5, [sp] // encoding: [0xe5,0x93,0x63,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+
+ rcwsclr x0, x1, [x4]
+// CHECK: rcwsclr x0, x1, [x4] // encoding: [0x81,0x90,0x20,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsclra x0, x1, [x4]
+// CHECK: rcwsclra x0, x1, [x4] // encoding: [0x81,0x90,0xa0,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsclral x0, x1, [x4]
+// CHECK: rcwsclral x0, x1, [x4] // encoding: [0x81,0x90,0xe0,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsclrl x0, x1, [x4]
+// CHECK: rcwsclrl x0, x1, [x4] // encoding: [0x81,0x90,0x60,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsclr x3, x5, [sp]
+// CHECK: rcwsclr x3, x5, [sp] // encoding: [0xe5,0x93,0x23,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsclra x3, x5, [sp]
+// CHECK: rcwsclra x3, x5, [sp] // encoding: [0xe5,0x93,0xa3,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsclral x3, x5, [sp]
+// CHECK: rcwsclral x3, x5, [sp] // encoding: [0xe5,0x93,0xe3,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsclrl x3, x5, [sp]
+// CHECK: rcwsclrl x3, x5, [sp] // encoding: [0xe5,0x93,0x63,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+
+ rcwclrp x1, x0, [x4]
+// CHECK: rcwclrp x1, x0, [x4] // encoding: [0x81,0x90,0x20,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwclrpa x1, x0, [x4]
+// CHECK: rcwclrpa x1, x0, [x4] // encoding: [0x81,0x90,0xa0,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwclrpal x1, x0, [x4]
+// CHECK: rcwclrpal x1, x0, [x4] // encoding: [0x81,0x90,0xe0,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwclrpl x1, x0, [x4]
+// CHECK: rcwclrpl x1, x0, [x4] // encoding: [0x81,0x90,0x60,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwclrp x5, x3, [sp]
+// CHECK: rcwclrp x5, x3, [sp] // encoding: [0xe5,0x93,0x23,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwclrpa x5, x3, [sp]
+// CHECK: rcwclrpa x5, x3, [sp] // encoding: [0xe5,0x93,0xa3,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwclrpal x5, x3, [sp]
+// CHECK: rcwclrpal x5, x3, [sp] // encoding: [0xe5,0x93,0xe3,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwclrpl x5, x3, [sp]
+// CHECK: rcwclrpl x5, x3, [sp] // encoding: [0xe5,0x93,0x63,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+
+ rcwsclrp x1, x0, [x4]
+// CHECK: rcwsclrp x1, x0, [x4] // encoding: [0x81,0x90,0x20,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsclrpa x1, x0, [x4]
+// CHECK: rcwsclrpa x1, x0, [x4] // encoding: [0x81,0x90,0xa0,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsclrpal x1, x0, [x4]
+// CHECK: rcwsclrpal x1, x0, [x4] // encoding: [0x81,0x90,0xe0,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsclrpl x1, x0, [x4]
+// CHECK: rcwsclrpl x1, x0, [x4] // encoding: [0x81,0x90,0x60,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsclrp x5, x3, [sp]
+// CHECK: rcwsclrp x5, x3, [sp] // encoding: [0xe5,0x93,0x23,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsclrpa x5, x3, [sp]
+// CHECK: rcwsclrpa x5, x3, [sp] // encoding: [0xe5,0x93,0xa3,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsclrpal x5, x3, [sp]
+// CHECK: rcwsclrpal x5, x3, [sp] // encoding: [0xe5,0x93,0xe3,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsclrpl x5, x3, [sp]
+// CHECK: rcwsclrpl x5, x3, [sp] // encoding: [0xe5,0x93,0x63,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+
+ rcwset x0, x1, [x4]
+// CHECK: rcwset x0, x1, [x4] // encoding: [0x81,0xb0,0x20,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwseta x0, x1, [x4]
+// CHECK: rcwseta x0, x1, [x4] // encoding: [0x81,0xb0,0xa0,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsetal x0, x1, [x4]
+// CHECK: rcwsetal x0, x1, [x4] // encoding: [0x81,0xb0,0xe0,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsetl x0, x1, [x4]
+// CHECK: rcwsetl x0, x1, [x4] // encoding: [0x81,0xb0,0x60,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwset x3, x5, [sp]
+// CHECK: rcwset x3, x5, [sp] // encoding: [0xe5,0xb3,0x23,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwseta x3, x5, [sp]
+// CHECK: rcwseta x3, x5, [sp] // encoding: [0xe5,0xb3,0xa3,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsetal x3, x5, [sp]
+// CHECK: rcwsetal x3, x5, [sp] // encoding: [0xe5,0xb3,0xe3,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsetl x3, x5, [sp]
+// CHECK: rcwsetl x3, x5, [sp] // encoding: [0xe5,0xb3,0x63,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+
+ rcwsset x0, x1, [x4]
+// CHECK: rcwsset x0, x1, [x4] // encoding: [0x81,0xb0,0x20,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsseta x0, x1, [x4]
+// CHECK: rcwsseta x0, x1, [x4] // encoding: [0x81,0xb0,0xa0,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwssetal x0, x1, [x4]
+// CHECK: rcwssetal x0, x1, [x4] // encoding: [0x81,0xb0,0xe0,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwssetl x0, x1, [x4]
+// CHECK: rcwssetl x0, x1, [x4] // encoding: [0x81,0xb0,0x60,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsset x3, x5, [sp]
+// CHECK: rcwsset x3, x5, [sp] // encoding: [0xe5,0xb3,0x23,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsseta x3, x5, [sp]
+// CHECK: rcwsseta x3, x5, [sp] // encoding: [0xe5,0xb3,0xa3,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwssetal x3, x5, [sp]
+// CHECK: rcwssetal x3, x5, [sp] // encoding: [0xe5,0xb3,0xe3,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwssetl x3, x5, [sp]
+// CHECK: rcwssetl x3, x5, [sp] // encoding: [0xe5,0xb3,0x63,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+
+ rcwsetp x1, x0, [x4]
+// CHECK: rcwsetp x1, x0, [x4] // encoding: [0x81,0xb0,0x20,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsetpa x1, x0, [x4]
+// CHECK: rcwsetpa x1, x0, [x4] // encoding: [0x81,0xb0,0xa0,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsetpal x1, x0, [x4]
+// CHECK: rcwsetpal x1, x0, [x4] // encoding: [0x81,0xb0,0xe0,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsetpl x1, x0, [x4]
+// CHECK: rcwsetpl x1, x0, [x4] // encoding: [0x81,0xb0,0x60,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsetp x5, x3, [sp]
+// CHECK: rcwsetp x5, x3, [sp] // encoding: [0xe5,0xb3,0x23,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsetpa x5, x3, [sp]
+// CHECK: rcwsetpa x5, x3, [sp] // encoding: [0xe5,0xb3,0xa3,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsetpal x5, x3, [sp]
+// CHECK: rcwsetpal x5, x3, [sp] // encoding: [0xe5,0xb3,0xe3,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsetpl x5, x3, [sp]
+// CHECK: rcwsetpl x5, x3, [sp] // encoding: [0xe5,0xb3,0x63,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+
+ rcwssetp x1, x0, [x4]
+// CHECK: rcwssetp x1, x0, [x4] // encoding: [0x81,0xb0,0x20,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwssetpa x1, x0, [x4]
+// CHECK: rcwssetpa x1, x0, [x4] // encoding: [0x81,0xb0,0xa0,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwssetpal x1, x0, [x4]
+// CHECK: rcwssetpal x1, x0, [x4] // encoding: [0x81,0xb0,0xe0,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwssetpl x1, x0, [x4]
+// CHECK: rcwssetpl x1, x0, [x4] // encoding: [0x81,0xb0,0x60,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwssetp x5, x3, [sp]
+// CHECK: rcwssetp x5, x3, [sp] // encoding: [0xe5,0xb3,0x23,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwssetpa x5, x3, [sp]
+// CHECK: rcwssetpa x5, x3, [sp] // encoding: [0xe5,0xb3,0xa3,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwssetpal x5, x3, [sp]
+// CHECK: rcwssetpal x5, x3, [sp] // encoding: [0xe5,0xb3,0xe3,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwssetpl x5, x3, [sp]
+// CHECK: rcwssetpl x5, x3, [sp] // encoding: [0xe5,0xb3,0x63,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+
+ rcwswp x0, x1, [x4]
+// CHECK: rcwswp x0, x1, [x4] // encoding: [0x81,0xa0,0x20,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwswpa x0, x1, [x4]
+// CHECK: rcwswpa x0, x1, [x4] // encoding: [0x81,0xa0,0xa0,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwswpal x0, x1, [x4]
+// CHECK: rcwswpal x0, x1, [x4] // encoding: [0x81,0xa0,0xe0,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwswpl x0, x1, [x4]
+// CHECK: rcwswpl x0, x1, [x4] // encoding: [0x81,0xa0,0x60,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwswp x3, x5, [sp]
+// CHECK: rcwswp x3, x5, [sp] // encoding: [0xe5,0xa3,0x23,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwswpa x3, x5, [sp]
+// CHECK: rcwswpa x3, x5, [sp] // encoding: [0xe5,0xa3,0xa3,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwswpal x3, x5, [sp]
+// CHECK: rcwswpal x3, x5, [sp] // encoding: [0xe5,0xa3,0xe3,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwswpl x3, x5, [sp]
+// CHECK: rcwswpl x3, x5, [sp] // encoding: [0xe5,0xa3,0x63,0x38]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+
+ rcwsswp x0, x1, [x4]
+// CHECK: rcwsswp x0, x1, [x4] // encoding: [0x81,0xa0,0x20,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsswpa x0, x1, [x4]
+// CHECK: rcwsswpa x0, x1, [x4] // encoding: [0x81,0xa0,0xa0,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsswpal x0, x1, [x4]
+// CHECK: rcwsswpal x0, x1, [x4] // encoding: [0x81,0xa0,0xe0,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsswpl x0, x1, [x4]
+// CHECK: rcwsswpl x0, x1, [x4] // encoding: [0x81,0xa0,0x60,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsswp x3, x5, [sp]
+// CHECK: rcwsswp x3, x5, [sp] // encoding: [0xe5,0xa3,0x23,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsswpa x3, x5, [sp]
+// CHECK: rcwsswpa x3, x5, [sp] // encoding: [0xe5,0xa3,0xa3,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsswpal x3, x5, [sp]
+// CHECK: rcwsswpal x3, x5, [sp] // encoding: [0xe5,0xa3,0xe3,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+ rcwsswpl x3, x5, [sp]
+// CHECK: rcwsswpl x3, x5, [sp] // encoding: [0xe5,0xa3,0x63,0x78]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the
+
+ rcwswpp x1, x0, [x4]
+// CHECK: rcwswpp x1, x0, [x4] // encoding: [0x81,0xa0,0x20,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwswppa x1, x0, [x4]
+// CHECK: rcwswppa x1, x0, [x4] // encoding: [0x81,0xa0,0xa0,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwswppal x1, x0, [x4]
+// CHECK: rcwswppal x1, x0, [x4] // encoding: [0x81,0xa0,0xe0,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwswppl x1, x0, [x4]
+// CHECK: rcwswppl x1, x0, [x4] // encoding: [0x81,0xa0,0x60,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwswpp x5, x3, [sp]
+// CHECK: rcwswpp x5, x3, [sp] // encoding: [0xe5,0xa3,0x23,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwswppa x5, x3, [sp]
+// CHECK: rcwswppa x5, x3, [sp] // encoding: [0xe5,0xa3,0xa3,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwswppal x5, x3, [sp]
+// CHECK: rcwswppal x5, x3, [sp] // encoding: [0xe5,0xa3,0xe3,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwswppl x5, x3, [sp]
+// CHECK: rcwswppl x5, x3, [sp] // encoding: [0xe5,0xa3,0x63,0x19]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+
+ rcwsswpp x1, x0, [x4]
+// CHECK: rcwsswpp x1, x0, [x4] // encoding: [0x81,0xa0,0x20,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsswppa x1, x0, [x4]
+// CHECK: rcwsswppa x1, x0, [x4] // encoding: [0x81,0xa0,0xa0,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsswppal x1, x0, [x4]
+// CHECK: rcwsswppal x1, x0, [x4] // encoding: [0x81,0xa0,0xe0,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsswppl x1, x0, [x4]
+// CHECK: rcwsswppl x1, x0, [x4] // encoding: [0x81,0xa0,0x60,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsswpp x5, x3, [sp]
+// CHECK: rcwsswpp x5, x3, [sp] // encoding: [0xe5,0xa3,0x23,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsswppa x5, x3, [sp]
+// CHECK: rcwsswppa x5, x3, [sp] // encoding: [0xe5,0xa3,0xa3,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsswppal x5, x3, [sp]
+// CHECK: rcwsswppal x5, x3, [sp] // encoding: [0xe5,0xa3,0xe3,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+ rcwsswppl x5, x3, [sp]
+// CHECK: rcwsswppl x5, x3, [sp] // encoding: [0xe5,0xa3,0x63,0x59]
+// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the
+// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128
+
+ rcwswpp xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction
+ rcwswppa xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction
+ rcwswppal xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction
+ rcwswppl xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction
+ rcwswpp x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction
+ rcwswppa x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction
+ rcwswppal x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction
+ rcwswppl x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction
+
+ rcwclrp xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction
+ rcwclrpa xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction
+ rcwclrpal xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction
+ rcwclrpl xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction
+ rcwclrp x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction
+ rcwclrpa x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction
+ rcwclrpal x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction
+ rcwclrpl x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction
+
+ rcwsetp xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction
+ rcwsetpa xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction
+ rcwsetpal xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction
+ rcwsetpl xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction
+ rcwsetp x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction
+ rcwsetpa x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction
+ rcwsetpal x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction
+ rcwsetpl x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction
+
+ rcwsswpp xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction
+ rcwsswppa xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction
+ rcwsswppal xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction
+ rcwsswppl xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction
+ rcwsswpp x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction
+ rcwsswppa x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction
+ rcwsswppal x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction
+ rcwsswppl x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction
+
+ rcwsclrp xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction
+ rcwsclrpa xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction
+ rcwsclrpal xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction
+ rcwsclrpl xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction
+ rcwsclrp x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction
+ rcwsclrpa x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction
+ rcwsclrpal x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction
+ rcwsclrpl x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction
+
+ rcwssetp xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction
+ rcwssetpa xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction
+ rcwssetpal xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction
+ rcwssetpl xzr, x5, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction
+ rcwssetp x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction
+ rcwssetpa x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction
+ rcwssetpal x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction
+ rcwssetpl x5, xzr, [x4]
+// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction
diff --git a/llvm/test/MC/AArch64/armv9-mrrs.s b/llvm/test/MC/AArch64/armv9-mrrs.s
new file mode 100644
index 0000000000000..870127826cb1f
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9-mrrs.s
@@ -0,0 +1,100 @@
+// +the required for RCWSMASK_EL1, RCWMASK_EL1
+// +el2vmsa required for TTBR0_EL2 (VSCTLR_EL2), VTTBR_EL2
+// +vh required for TTBR1_EL2
+
+// RUN: not llvm-mc -triple aarch64 -mattr=+d128,+the,+el2vmsa,+vh -show-encoding %s -o - 2> %t | FileCheck %s
+// RUN: FileCheck %s --input-file=%t --check-prefix=ERRORS
+
+// RUN: not llvm-mc -triple aarch64 -mattr=+the,+el2vmsa,+vh -show-encoding %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128
+
+ mrrs x0, x1, TTBR0_EL1
+// CHECK: mrrs x0, x1, TTBR0_EL1 // encoding: [0x00,0x20,0x78,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x0, x1, TTBR1_EL1
+// CHECK: mrrs x0, x1, TTBR1_EL1 // encoding: [0x20,0x20,0x78,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x0, x1, PAR_EL1
+// CHECK: mrrs x0, x1, PAR_EL1 // encoding: [0x00,0x74,0x78,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x0, x1, RCWSMASK_EL1
+// CHECK: mrrs x0, x1, RCWSMASK_EL1 // encoding: [0x60,0xd0,0x78,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x0, x1, RCWMASK_EL1
+// CHECK: mrrs x0, x1, RCWMASK_EL1 // encoding: [0xc0,0xd0,0x78,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x0, x1, TTBR0_EL2
+// CHECK: mrrs x0, x1, TTBR0_EL2 // encoding: [0x00,0x20,0x7c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x0, x1, TTBR1_EL2
+// CHECK: mrrs x0, x1, TTBR1_EL2 // encoding: [0x20,0x20,0x7c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x0, x1, VTTBR_EL2
+// CHECK: mrrs x0, x1, VTTBR_EL2 // encoding: [0x00,0x21,0x7c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+
+ mrrs x0, x1, VTTBR_EL2
+// CHECK: mrrs x0, x1, VTTBR_EL2 // encoding: [0x00,0x21,0x7c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x2, x3, VTTBR_EL2
+// CHECK: mrrs x2, x3, VTTBR_EL2 // encoding: [0x02,0x21,0x7c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x4, x5, VTTBR_EL2
+// CHECK: mrrs x4, x5, VTTBR_EL2 // encoding: [0x04,0x21,0x7c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x6, x7, VTTBR_EL2
+// CHECK: mrrs x6, x7, VTTBR_EL2 // encoding: [0x06,0x21,0x7c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x8, x9, VTTBR_EL2
+// CHECK: mrrs x8, x9, VTTBR_EL2 // encoding: [0x08,0x21,0x7c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x10, x11, VTTBR_EL2
+// CHECK: mrrs x10, x11, VTTBR_EL2 // encoding: [0x0a,0x21,0x7c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x12, x13, VTTBR_EL2
+// CHECK: mrrs x12, x13, VTTBR_EL2 // encoding: [0x0c,0x21,0x7c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x14, x15, VTTBR_EL2
+// CHECK: mrrs x14, x15, VTTBR_EL2 // encoding: [0x0e,0x21,0x7c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x16, x17, VTTBR_EL2
+// CHECK: mrrs x16, x17, VTTBR_EL2 // encoding: [0x10,0x21,0x7c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x18, x19, VTTBR_EL2
+// CHECK: mrrs x18, x19, VTTBR_EL2 // encoding: [0x12,0x21,0x7c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x20, x21, VTTBR_EL2
+// CHECK: mrrs x20, x21, VTTBR_EL2 // encoding: [0x14,0x21,0x7c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x22, x23, VTTBR_EL2
+// CHECK: mrrs x22, x23, VTTBR_EL2 // encoding: [0x16,0x21,0x7c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x24, x25, VTTBR_EL2
+// CHECK: mrrs x24, x25, VTTBR_EL2 // encoding: [0x18,0x21,0x7c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ mrrs x26, x27, VTTBR_EL2
+// CHECK: mrrs x26, x27, VTTBR_EL2 // encoding: [0x1a,0x21,0x7c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+
+ mrrs x0, x2, TTBR0_EL1
+// ERRORS: error: expected second odd register of a consecutive same-size even/odd register pair
+
+ mrrs x0, TTBR0_EL1
+// ERRORS: error: expected second odd register of a consecutive same-size even/odd register pair
+
+ mrrs x1, x2, TTBR0_EL1
+// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair
+
+ mrrs x31, x0, TTBR0_EL1
+// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair
+
+ mrrs xzr, x30, TTBR0_EL1
+// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair
+
+ mrrs xzr, TTBR0_EL1
+// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair
+
+ mrrs S3_0_c2_c0_1
+// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair
+
+ mrrs S3_0_c2_c0_1, x0, x1
+// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair
diff --git a/llvm/test/MC/AArch64/armv9-msrr.s b/llvm/test/MC/AArch64/armv9-msrr.s
new file mode 100644
index 0000000000000..2be17a71e7d47
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9-msrr.s
@@ -0,0 +1,100 @@
+// +the required for RCWSMASK_EL1, RCWMASK_EL1
+// +el2vmsa required for TTBR0_EL2 (VSCTLR_EL2), VTTBR_EL2
+// +vh required for TTBR1_EL2
+
+// RUN: not llvm-mc -triple aarch64 -mattr=+d128,+the,+el2vmsa,+vh -show-encoding %s -o - 2> %t | FileCheck %s
+// RUN: FileCheck %s --input-file=%t --check-prefix=ERRORS
+
+// RUN: not llvm-mc -triple aarch64 -mattr=+the,+el2vmsa,+vh -show-encoding %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128
+
+ msrr TTBR0_EL1, x0, x1
+// CHECK: msrr TTBR0_EL1, x0, x1 // encoding: [0x00,0x20,0x58,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr TTBR1_EL1, x0, x1
+// CHECK: msrr TTBR1_EL1, x0, x1 // encoding: [0x20,0x20,0x58,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr PAR_EL1, x0, x1
+// CHECK: msrr PAR_EL1, x0, x1 // encoding: [0x00,0x74,0x58,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr RCWSMASK_EL1, x0, x1
+// CHECK: msrr RCWSMASK_EL1, x0, x1 // encoding: [0x60,0xd0,0x58,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr RCWMASK_EL1, x0, x1
+// CHECK: msrr RCWMASK_EL1, x0, x1 // encoding: [0xc0,0xd0,0x58,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr TTBR0_EL2, x0, x1
+// CHECK: msrr TTBR0_EL2, x0, x1 // encoding: [0x00,0x20,0x5c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr TTBR1_EL2, x0, x1
+// CHECK: msrr TTBR1_EL2, x0, x1 // encoding: [0x20,0x20,0x5c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr VTTBR_EL2, x0, x1
+// CHECK: msrr VTTBR_EL2, x0, x1 // encoding: [0x00,0x21,0x5c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+
+ msrr VTTBR_EL2, x0, x1
+// CHECK: msrr VTTBR_EL2, x0, x1 // encoding: [0x00,0x21,0x5c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr VTTBR_EL2, x2, x3
+// CHECK: msrr VTTBR_EL2, x2, x3 // encoding: [0x02,0x21,0x5c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr VTTBR_EL2, x4, x5
+// CHECK: msrr VTTBR_EL2, x4, x5 // encoding: [0x04,0x21,0x5c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr VTTBR_EL2, x6, x7
+// CHECK: msrr VTTBR_EL2, x6, x7 // encoding: [0x06,0x21,0x5c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr VTTBR_EL2, x8, x9
+// CHECK: msrr VTTBR_EL2, x8, x9 // encoding: [0x08,0x21,0x5c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr VTTBR_EL2, x10, x11
+// CHECK: msrr VTTBR_EL2, x10, x11 // encoding: [0x0a,0x21,0x5c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr VTTBR_EL2, x12, x13
+// CHECK: msrr VTTBR_EL2, x12, x13 // encoding: [0x0c,0x21,0x5c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr VTTBR_EL2, x14, x15
+// CHECK: msrr VTTBR_EL2, x14, x15 // encoding: [0x0e,0x21,0x5c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr VTTBR_EL2, x16, x17
+// CHECK: msrr VTTBR_EL2, x16, x17 // encoding: [0x10,0x21,0x5c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr VTTBR_EL2, x18, x19
+// CHECK: msrr VTTBR_EL2, x18, x19 // encoding: [0x12,0x21,0x5c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr VTTBR_EL2, x20, x21
+// CHECK: msrr VTTBR_EL2, x20, x21 // encoding: [0x14,0x21,0x5c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr VTTBR_EL2, x22, x23
+// CHECK: msrr VTTBR_EL2, x22, x23 // encoding: [0x16,0x21,0x5c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr VTTBR_EL2, x24, x25
+// CHECK: msrr VTTBR_EL2, x24, x25 // encoding: [0x18,0x21,0x5c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ msrr VTTBR_EL2, x26, x27
+// CHECK: msrr VTTBR_EL2, x26, x27 // encoding: [0x1a,0x21,0x5c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+
+ msrr TTBR0_EL1, x0, x2
+// ERRORS: error: expected second odd register of a consecutive same-size even/odd register pair
+
+ msrr TTBR0_EL1, x0
+// ERRORS: error: expected comma
+
+ msrr TTBR0_EL1, x1, x2
+// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair
+
+ msrr TTBR0_EL1, x31, x0
+// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair
+
+ msrr TTBR0_EL1, xzr, x30
+// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair
+
+ msrr TTBR0_EL1, xzr
+// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair
+
+ msrr S3_0_c2_c0_1
+// ERRORS: error: too few operands for instruction
+
+ msrr x0, x1, S3_0_c2_c0_1
+// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair
diff --git a/llvm/test/MC/AArch64/armv9-sysp.s b/llvm/test/MC/AArch64/armv9-sysp.s
new file mode 100644
index 0000000000000..908e880ad0aa4
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9-sysp.s
@@ -0,0 +1,538 @@
+// +tbl-rmi required for RIPA*/RVA*
+// +xs required for *NXS
+
+// RUN: not llvm-mc -triple aarch64 -mattr=+d128,+tlb-rmi,+xs -show-encoding %s -o - 2> %t | FileCheck %s
+// RUN: FileCheck %s --input-file=%t --check-prefix=ERRORS
+
+// RUN: not llvm-mc -triple aarch64 -mattr=+tlb-rmi,+xs -show-encoding %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128
+
+// sysp #<op1>, <Cn>, <Cm>, #<op2>{, <Xt1>, <Xt2>}
+// registers with 128-bit formats (op0, op1, Cn, Cm, op2)
+// For sysp, op0 is 0
+
+ sysp #0, c2, c0, #0, x0, x1 // TTBR0_EL1 3 0 2 0 0
+// CHECK: sysp #0, c2, c0, #0, x0, x1 // encoding: [0x00,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #1, x0, x1 // TTBR1_EL1 3 0 2 0 1
+// CHECK: sysp #0, c2, c0, #1, x0, x1 // encoding: [0x20,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c7, c4, #0, x0, x1 // PAR_EL1 3 0 7 4 0
+// CHECK: sysp #0, c7, c4, #0, x0, x1 // encoding: [0x00,0x74,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c13, c0, #3, x0, x1 // RCWSMASK_EL1 3 0 13 0 3
+// CHECK: sysp #0, c13, c0, #3, x0, x1 // encoding: [0x60,0xd0,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c13, c0, #6, x0, x1 // RCWMASK_EL1 3 0 13 0 6
+// CHECK: sysp #0, c13, c0, #6, x0, x1 // encoding: [0xc0,0xd0,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #4, c2, c0, #0, x0, x1 // TTBR0_EL2 3 4 2 0 0
+// CHECK: sysp #4, c2, c0, #0, x0, x1 // encoding: [0x00,0x20,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #4, c2, c0, #1, x0, x1 // TTBR1_EL2 3 4 2 0 1
+// CHECK: sysp #4, c2, c0, #1, x0, x1 // encoding: [0x20,0x20,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #4, c2, c1, #0, x0, x1 // VTTBR_EL2 3 4 2 1 0
+// CHECK: sysp #4, c2, c1, #0, x0, x1 // encoding: [0x00,0x21,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+
+
+ sysp #0, c2, c0, #0, x0, x1
+// CHECK: sysp #0, c2, c0, #0, x0, x1 // encoding: [0x00,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #1, x0, x1
+// CHECK: sysp #0, c2, c0, #1, x0, x1 // encoding: [0x20,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c7, c4, #0, x0, x1
+// CHECK: sysp #0, c7, c4, #0, x0, x1 // encoding: [0x00,0x74,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c13, c0, #3, x0, x1
+// CHECK: sysp #0, c13, c0, #3, x0, x1 // encoding: [0x60,0xd0,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c13, c0, #6, x0, x1
+// CHECK: sysp #0, c13, c0, #6, x0, x1 // encoding: [0xc0,0xd0,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #4, c2, c0, #0, x0, x1
+// CHECK: sysp #4, c2, c0, #0, x0, x1 // encoding: [0x00,0x20,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #4, c2, c0, #1, x0, x1
+// CHECK: sysp #4, c2, c0, #1, x0, x1 // encoding: [0x20,0x20,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #4, c2, c1, #0, x0, x1
+// CHECK: sysp #4, c2, c1, #0, x0, x1 // encoding: [0x00,0x21,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+
+ sysp #0, c2, c0, #0, x0, x1
+// CHECK: sysp #0, c2, c0, #0, x0, x1 // encoding: [0x00,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, x2, x3
+// CHECK: sysp #0, c2, c0, #0, x2, x3 // encoding: [0x02,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, x4, x5
+// CHECK: sysp #0, c2, c0, #0, x4, x5 // encoding: [0x04,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, x6, x7
+// CHECK: sysp #0, c2, c0, #0, x6, x7 // encoding: [0x06,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, x8, x9
+// CHECK: sysp #0, c2, c0, #0, x8, x9 // encoding: [0x08,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, x10, x11
+// CHECK: sysp #0, c2, c0, #0, x10, x11 // encoding: [0x0a,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, x12, x13
+// CHECK: sysp #0, c2, c0, #0, x12, x13 // encoding: [0x0c,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, x14, x15
+// CHECK: sysp #0, c2, c0, #0, x14, x15 // encoding: [0x0e,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, x16, x17
+// CHECK: sysp #0, c2, c0, #0, x16, x17 // encoding: [0x10,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, x18, x19
+// CHECK: sysp #0, c2, c0, #0, x18, x19 // encoding: [0x12,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, x20, x21
+// CHECK: sysp #0, c2, c0, #0, x20, x21 // encoding: [0x14,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, x22, x23
+// CHECK: sysp #0, c2, c0, #0, x22, x23 // encoding: [0x16,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, x24, x25
+// CHECK: sysp #0, c2, c0, #0, x24, x25 // encoding: [0x18,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, x26, x27
+// CHECK: sysp #0, c2, c0, #0, x26, x27 // encoding: [0x1a,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, x28, x29
+// CHECK: sysp #0, c2, c0, #0, x28, x29 // encoding: [0x1c,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, x30, x31
+// CHECK: sysp #0, c2, c0, #0, x30, xzr // encoding: [0x1e,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+
+ sysp #0, c2, c0, #0, x31, x31
+// CHECK: sysp #0, c2, c0, #0 // encoding: [0x1f,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, xzr, xzr
+// CHECK: sysp #0, c2, c0, #0 // encoding: [0x1f,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, x31, xzr
+// CHECK: sysp #0, c2, c0, #0 // encoding: [0x1f,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0, xzr, x31
+// CHECK: sysp #0, c2, c0, #0 // encoding: [0x1f,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ sysp #0, c2, c0, #0
+// CHECK: sysp #0, c2, c0, #0 // encoding: [0x1f,0x20,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+
+
+ sysp #0, c2, c0, #0, x0, x2
+// ERRORS: error: expected second odd register of a consecutive same-size even/odd register pair
+
+ sysp #0, c2, c0, #0, x0
+// ERRORS: error: expected comma
+
+ sysp #0, c2, c0, #0, x1, x2
+// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair
+
+ sysp #0, c2, c0, #0, x31, x0
+// ERRORS: error: xzr must be followed by xzr
+
+ sysp #0, c2, c0, #0, xzr, x30
+// ERRORS: error: xzr must be followed by xzr
+
+ sysp #0, c2, c0, #0, xzr
+// ERRORS: error: expected comma
+
+ sysp #0, c2, c0, #0, xzr,
+// ERRORS: error: expected register operand
+
+
+ tlbip IPAS2E1, x4, x5
+// CHECK: tlbip ipas2e1, x4, x5 // encoding: [0x24,0x84,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip IPAS2E1NXS, x4, x5
+// CHECK: tlbip ipas2e1nxs, x4, x5 // encoding: [0x24,0x94,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip IPAS2E1IS, x4, x5
+// CHECK: tlbip ipas2e1is, x4, x5 // encoding: [0x24,0x80,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip IPAS2E1ISNXS, x4, x5
+// CHECK: tlbip ipas2e1isnxs, x4, x5 // encoding: [0x24,0x90,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip IPAS2E1OS, x4, x5
+// CHECK: tlbip ipas2e1os, x4, x5 // encoding: [0x04,0x84,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip IPAS2E1OSNXS, x4, x5
+// CHECK: tlbip ipas2e1osnxs, x4, x5 // encoding: [0x04,0x94,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip IPAS2LE1, x4, x5
+// CHECK: tlbip ipas2le1, x4, x5 // encoding: [0xa4,0x84,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip IPAS2LE1NXS, x4, x5
+// CHECK: tlbip ipas2le1nxs, x4, x5 // encoding: [0xa4,0x94,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip IPAS2LE1IS, x4, x5
+// CHECK: tlbip ipas2le1is, x4, x5 // encoding: [0xa4,0x80,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip IPAS2LE1ISNXS, x4, x5
+// CHECK: tlbip ipas2le1isnxs, x4, x5 // encoding: [0xa4,0x90,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip IPAS2LE1OS, x4, x5
+// CHECK: tlbip ipas2le1os, x4, x5 // encoding: [0x84,0x84,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip IPAS2LE1OSNXS, x4, x5
+// CHECK: tlbip ipas2le1osnxs, x4, x5 // encoding: [0x84,0x94,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+
+
+ tlbip VAE1, x8, x9
+// CHECK: tlbip vae1, x8, x9 // encoding: [0x28,0x87,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAE1NXS, x8, x9
+// CHECK: tlbip vae1nxs, x8, x9 // encoding: [0x28,0x97,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAE1IS, x8, x9
+// CHECK: tlbip vae1is, x8, x9 // encoding: [0x28,0x83,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAE1ISNXS, x8, x9
+// CHECK: tlbip vae1isnxs, x8, x9 // encoding: [0x28,0x93,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAE1OS, x8, x9
+// CHECK: tlbip vae1os, x8, x9 // encoding: [0x28,0x81,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAE1OSNXS, x8, x9
+// CHECK: tlbip vae1osnxs, x8, x9 // encoding: [0x28,0x91,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE1, x8, x9
+// CHECK: tlbip vale1, x8, x9 // encoding: [0xa8,0x87,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE1NXS, x8, x9
+// CHECK: tlbip vale1nxs, x8, x9 // encoding: [0xa8,0x97,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE1IS, x8, x9
+// CHECK: tlbip vale1is, x8, x9 // encoding: [0xa8,0x83,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE1ISNXS, x8, x9
+// CHECK: tlbip vale1isnxs, x8, x9 // encoding: [0xa8,0x93,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE1OS, x8, x9
+// CHECK: tlbip vale1os, x8, x9 // encoding: [0xa8,0x81,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE1OSNXS, x8, x9
+// CHECK: tlbip vale1osnxs, x8, x9 // encoding: [0xa8,0x91,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAAE1, x8, x9
+// CHECK: tlbip vaae1, x8, x9 // encoding: [0x68,0x87,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAAE1NXS, x8, x9
+// CHECK: tlbip vaae1nxs, x8, x9 // encoding: [0x68,0x97,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAAE1IS, x8, x9
+// CHECK: tlbip vaae1is, x8, x9 // encoding: [0x68,0x83,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAAE1ISNXS, x8, x9
+// CHECK: tlbip vaae1isnxs, x8, x9 // encoding: [0x68,0x93,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAAE1OS, x8, x9
+// CHECK: tlbip vaae1os, x8, x9 // encoding: [0x68,0x81,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAAE1OSNXS, x8, x9
+// CHECK: tlbip vaae1osnxs, x8, x9 // encoding: [0x68,0x91,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAALE1, x8, x9
+// CHECK: tlbip vaale1, x8, x9 // encoding: [0xe8,0x87,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAALE1NXS, x8, x9
+// CHECK: tlbip vaale1nxs, x8, x9 // encoding: [0xe8,0x97,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAALE1IS, x8, x9
+// CHECK: tlbip vaale1is, x8, x9 // encoding: [0xe8,0x83,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAALE1ISNXS, x8, x9
+// CHECK: tlbip vaale1isnxs, x8, x9 // encoding: [0xe8,0x93,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAALE1OS, x8, x9
+// CHECK: tlbip vaale1os, x8, x9 // encoding: [0xe8,0x81,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAALE1OSNXS, x8, x9
+// CHECK: tlbip vaale1osnxs, x8, x9 // encoding: [0xe8,0x91,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+
+ tlbip VAE2, x14, x15
+// CHECK: tlbip vae2, x14, x15 // encoding: [0x2e,0x87,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAE2NXS, x14, x15
+// CHECK: tlbip vae2nxs, x14, x15 // encoding: [0x2e,0x97,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAE2IS, x14, x15
+// CHECK: tlbip vae2is, x14, x15 // encoding: [0x2e,0x83,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAE2ISNXS, x14, x15
+// CHECK: tlbip vae2isnxs, x14, x15 // encoding: [0x2e,0x93,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAE2OS, x14, x15
+// CHECK: tlbip vae2os, x14, x15 // encoding: [0x2e,0x81,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAE2OSNXS, x14, x15
+// CHECK: tlbip vae2osnxs, x14, x15 // encoding: [0x2e,0x91,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE2, x14, x15
+// CHECK: tlbip vale2, x14, x15 // encoding: [0xae,0x87,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE2NXS, x14, x15
+// CHECK: tlbip vale2nxs, x14, x15 // encoding: [0xae,0x97,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE2IS, x14, x15
+// CHECK: tlbip vale2is, x14, x15 // encoding: [0xae,0x83,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE2ISNXS, x14, x15
+// CHECK: tlbip vale2isnxs, x14, x15 // encoding: [0xae,0x93,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE2OS, x14, x15
+// CHECK: tlbip vale2os, x14, x15 // encoding: [0xae,0x81,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE2OSNXS, x14, x15
+// CHECK: tlbip vale2osnxs, x14, x15 // encoding: [0xae,0x91,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+
+ tlbip VAE3, x24, x25
+// CHECK: tlbip vae3, x24, x25 // encoding: [0x38,0x87,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAE3NXS, x24, x25
+// CHECK: tlbip vae3nxs, x24, x25 // encoding: [0x38,0x97,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAE3IS, x24, x25
+// CHECK: tlbip vae3is, x24, x25 // encoding: [0x38,0x83,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAE3ISNXS, x24, x25
+// CHECK: tlbip vae3isnxs, x24, x25 // encoding: [0x38,0x93,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAE3OS, x24, x25
+// CHECK: tlbip vae3os, x24, x25 // encoding: [0x38,0x81,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VAE3OSNXS, x24, x25
+// CHECK: tlbip vae3osnxs, x24, x25 // encoding: [0x38,0x91,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE3, x24, x25
+// CHECK: tlbip vale3, x24, x25 // encoding: [0xb8,0x87,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE3NXS, x24, x25
+// CHECK: tlbip vale3nxs, x24, x25 // encoding: [0xb8,0x97,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE3IS, x24, x25
+// CHECK: tlbip vale3is, x24, x25 // encoding: [0xb8,0x83,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE3ISNXS, x24, x25
+// CHECK: tlbip vale3isnxs, x24, x25 // encoding: [0xb8,0x93,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE3OS, x24, x25
+// CHECK: tlbip vale3os, x24, x25 // encoding: [0xb8,0x81,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip VALE3OSNXS, x24, x25
+// CHECK: tlbip vale3osnxs, x24, x25 // encoding: [0xb8,0x91,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+
+
+ tlbip RVAE1, x18, x19
+// CHECK: tlbip rvae1, x18, x19 // encoding: [0x32,0x86,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAE1NXS, x18, x19
+// CHECK: tlbip rvae1nxs, x18, x19 // encoding: [0x32,0x96,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAE1IS, x18, x19
+// CHECK: tlbip rvae1is, x18, x19 // encoding: [0x32,0x82,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAE1ISNXS, x18, x19
+// CHECK: tlbip rvae1isnxs, x18, x19 // encoding: [0x32,0x92,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAE1OS, x18, x19
+// CHECK: tlbip rvae1os, x18, x19 // encoding: [0x32,0x85,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAE1OSNXS, x18, x19
+// CHECK: tlbip rvae1osnxs, x18, x19 // encoding: [0x32,0x95,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAAE1, x18, x19
+// CHECK: tlbip rvaae1, x18, x19 // encoding: [0x72,0x86,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAAE1NXS, x18, x19
+// CHECK: tlbip rvaae1nxs, x18, x19 // encoding: [0x72,0x96,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAAE1IS, x18, x19
+// CHECK: tlbip rvaae1is, x18, x19 // encoding: [0x72,0x82,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAAE1ISNXS, x18, x19
+// CHECK: tlbip rvaae1isnxs, x18, x19 // encoding: [0x72,0x92,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAAE1OS, x18, x19
+// CHECK: tlbip rvaae1os, x18, x19 // encoding: [0x72,0x85,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAAE1OSNXS, x18, x19
+// CHECK: tlbip rvaae1osnxs, x18, x19 // encoding: [0x72,0x95,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE1, x18, x19
+// CHECK: tlbip rvale1, x18, x19 // encoding: [0xb2,0x86,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE1NXS, x18, x19
+// CHECK: tlbip rvale1nxs, x18, x19 // encoding: [0xb2,0x96,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE1IS, x18, x19
+// CHECK: tlbip rvale1is, x18, x19 // encoding: [0xb2,0x82,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE1ISNXS, x18, x19
+// CHECK: tlbip rvale1isnxs, x18, x19 // encoding: [0xb2,0x92,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE1OS, x18, x19
+// CHECK: tlbip rvale1os, x18, x19 // encoding: [0xb2,0x85,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE1OSNXS, x18, x19
+// CHECK: tlbip rvale1osnxs, x18, x19 // encoding: [0xb2,0x95,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAALE1, x18, x19
+// CHECK: tlbip rvaale1, x18, x19 // encoding: [0xf2,0x86,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAALE1NXS, x18, x19
+// CHECK: tlbip rvaale1nxs, x18, x19 // encoding: [0xf2,0x96,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAALE1IS, x18, x19
+// CHECK: tlbip rvaale1is, x18, x19 // encoding: [0xf2,0x82,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAALE1ISNXS, x18, x19
+// CHECK: tlbip rvaale1isnxs, x18, x19 // encoding: [0xf2,0x92,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAALE1OS, x18, x19
+// CHECK: tlbip rvaale1os, x18, x19 // encoding: [0xf2,0x85,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAALE1OSNXS, x18, x19
+// CHECK: tlbip rvaale1osnxs, x18, x19 // encoding: [0xf2,0x95,0x48,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+
+ tlbip RVAE2, x28, x29
+// CHECK: tlbip rvae2, x28, x29 // encoding: [0x3c,0x86,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAE2NXS, x28, x29
+// CHECK: tlbip rvae2nxs, x28, x29 // encoding: [0x3c,0x96,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAE2IS, x28, x29
+// CHECK: tlbip rvae2is, x28, x29 // encoding: [0x3c,0x82,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAE2ISNXS, x28, x29
+// CHECK: tlbip rvae2isnxs, x28, x29 // encoding: [0x3c,0x92,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAE2OS, x28, x29
+// CHECK: tlbip rvae2os, x28, x29 // encoding: [0x3c,0x85,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAE2OSNXS, x28, x29
+// CHECK: tlbip rvae2osnxs, x28, x29 // encoding: [0x3c,0x95,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE2, x28, x29
+// CHECK: tlbip rvale2, x28, x29 // encoding: [0xbc,0x86,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE2NXS, x28, x29
+// CHECK: tlbip rvale2nxs, x28, x29 // encoding: [0xbc,0x96,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE2IS, x28, x29
+// CHECK: tlbip rvale2is, x28, x29 // encoding: [0xbc,0x82,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE2ISNXS, x28, x29
+// CHECK: tlbip rvale2isnxs, x28, x29 // encoding: [0xbc,0x92,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE2OS, x28, x29
+// CHECK: tlbip rvale2os, x28, x29 // encoding: [0xbc,0x85,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE2OSNXS, x28, x29
+// CHECK: tlbip rvale2osnxs, x28, x29 // encoding: [0xbc,0x95,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+
+ tlbip RVAE3, x10, x11
+// CHECK: tlbip rvae3, x10, x11 // encoding: [0x2a,0x86,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAE3NXS, x10, x11
+// CHECK: tlbip rvae3nxs, x10, x11 // encoding: [0x2a,0x96,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAE3IS, x10, x11
+// CHECK: tlbip rvae3is, x10, x11 // encoding: [0x2a,0x82,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAE3ISNXS, x10, x11
+// CHECK: tlbip rvae3isnxs, x10, x11 // encoding: [0x2a,0x92,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAE3OS, x10, x11
+// CHECK: tlbip rvae3os, x10, x11 // encoding: [0x2a,0x85,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAE3OSNXS, x10, x11
+// CHECK: tlbip rvae3osnxs, x10, x11 // encoding: [0x2a,0x95,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE3, x10, x11
+// CHECK: tlbip rvale3, x10, x11 // encoding: [0xaa,0x86,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE3NXS, x10, x11
+// CHECK: tlbip rvale3nxs, x10, x11 // encoding: [0xaa,0x96,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE3IS, x10, x11
+// CHECK: tlbip rvale3is, x10, x11 // encoding: [0xaa,0x82,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE3ISNXS, x10, x11
+// CHECK: tlbip rvale3isnxs, x10, x11 // encoding: [0xaa,0x92,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE3OS, x10, x11
+// CHECK: tlbip rvale3os, x10, x11 // encoding: [0xaa,0x85,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVALE3OSNXS, x10, x11
+// CHECK: tlbip rvale3osnxs, x10, x11 // encoding: [0xaa,0x95,0x4e,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+
+
+ tlbip RIPAS2E1, x20, x21
+// CHECK: tlbip ripas2e1, x20, x21 // encoding: [0x54,0x84,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RIPAS2E1NXS, x20, x21
+// CHECK: tlbip ripas2e1nxs, x20, x21 // encoding: [0x54,0x94,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RIPAS2E1IS, x20, x21
+// CHECK: tlbip ripas2e1is, x20, x21 // encoding: [0x54,0x80,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RIPAS2E1ISNXS, x20, x21
+// CHECK: tlbip ripas2e1isnxs, x20, x21 // encoding: [0x54,0x90,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RIPAS2E1OS, x20, x21
+// CHECK: tlbip ripas2e1os, x20, x21 // encoding: [0x74,0x84,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RIPAS2E1OSNXS, x20, x21
+// CHECK: tlbip ripas2e1osnxs, x20, x21 // encoding: [0x74,0x94,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RIPAS2LE1, x20, x21
+// CHECK: tlbip ripas2le1, x20, x21 // encoding: [0xd4,0x84,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RIPAS2LE1NXS, x20, x21
+// CHECK: tlbip ripas2le1nxs, x20, x21 // encoding: [0xd4,0x94,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RIPAS2LE1IS, x20, x21
+// CHECK: tlbip ripas2le1is, x20, x21 // encoding: [0xd4,0x80,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RIPAS2LE1ISNXS, x20, x21
+// CHECK: tlbip ripas2le1isnxs, x20, x21 // encoding: [0xd4,0x90,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RIPAS2LE1OS, x20, x21
+// CHECK: tlbip ripas2le1os, x20, x21 // encoding: [0xf4,0x84,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RIPAS2LE1OSNXS, x20, x21
+// CHECK: tlbip ripas2le1osnxs, x20, x21 // encoding: [0xf4,0x94,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+
+ tlbip RIPAS2LE1OS, xzr, xzr
+// CHECK: tlbip ripas2le1os, xzr, xzr // encoding: [0xff,0x84,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RIPAS2LE1OSNXS, xzr, xzr
+// CHECK: tlbip ripas2le1osnxs, xzr, xzr // encoding: [0xff,0x94,0x4c,0xd5]
+// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
+ tlbip RVAE3IS
+// ERRORS: error: expected comma
+ tlbip RVAE3IS,
+// ERRORS: error: expected register identifier
+ tlbip VAE3,
+// ERRORS: error: expected register identifier
+ tlbip IPAS2E1, x4, x8
+// ERRORS: error: specified tlbip op requires a pair of registers
+ tlbip RVAE3, x11, x11
+// ERRORS: error: specified tlbip op requires a pair of registers
diff --git a/llvm/test/MC/AArch64/armv9.4-lse128.s b/llvm/test/MC/AArch64/armv9.4-lse128.s
new file mode 100644
index 0000000000000..a639278ec8263
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9.4-lse128.s
@@ -0,0 +1,98 @@
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr +lse128 %s 2>%t | FileCheck %s
+// RUN: FileCheck %s --input-file=%t --check-prefix=ERROR-INVALID-OP
+// RUN: not llvm-mc -triple aarch64 -show-encoding %s 2>&1 | FileCheck --check-prefix=ERROR-NO-LSE128 %s
+
+ldclrp x1, x2, [x11]
+// CHECK: ldclrp x1, x2, [x11] // encoding: [0x61,0x11,0x22,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+ldclrp x21, x22, [sp]
+// CHECK: ldclrp x21, x22, [sp] // encoding: [0xf5,0x13,0x36,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+ldclrpa x1, x2, [x11]
+// CHECK: ldclrpa x1, x2, [x11] // encoding: [0x61,0x11,0xa2,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+ldclrpa x21, x22, [sp]
+// CHECK: ldclrpa x21, x22, [sp] // encoding: [0xf5,0x13,0xb6,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+ldclrpal x1, x2, [x11]
+// CHECK: ldclrpal x1, x2, [x11] // encoding: [0x61,0x11,0xe2,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+ldclrpal x21, x22, [sp]
+// CHECK: ldclrpal x21, x22, [sp] // encoding: [0xf5,0x13,0xf6,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+ldclrpl x1, x2, [x11]
+// CHECK: ldclrpl x1, x2, [x11] // encoding: [0x61,0x11,0x62,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+ldclrpl x21, x22, [sp]
+// CHECK: ldclrpl x21, x22, [sp] // encoding: [0xf5,0x13,0x76,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+ldclrpl x22, xzr, [sp]
+// ERROR-INVALID-OP: [[@LINE-1]]:15: error: invalid operand for instruction
+// ERROR-NO-LSE128: error: invalid operand for instruction
+ldclrpl xzr, x22, [sp]
+// ERROR-INVALID-OP: [[@LINE-1]]:10: error: invalid operand for instruction
+// ERROR-NO-LSE128: error: invalid operand for instruction
+
+ldsetp x1, x2, [x11]
+// CHECK: ldsetp x1, x2, [x11] // encoding: [0x61,0x31,0x22,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+ldsetp x21, x22, [sp]
+// CHECK: ldsetp x21, x22, [sp] // encoding: [0xf5,0x33,0x36,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+ldsetpa x1, x2, [x11]
+// CHECK: ldsetpa x1, x2, [x11] // encoding: [0x61,0x31,0xa2,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+ldsetpa x21, x22, [sp]
+// CHECK: ldsetpa x21, x22, [sp] // encoding: [0xf5,0x33,0xb6,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+ldsetpal x1, x2, [x11]
+// CHECK: ldsetpal x1, x2, [x11] // encoding: [0x61,0x31,0xe2,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+ldsetpal x21, x22, [sp]
+// CHECK: ldsetpal x21, x22, [sp] // encoding: [0xf5,0x33,0xf6,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+ldsetpl x1, x2, [x11]
+// CHECK: ldsetpl x1, x2, [x11] // encoding: [0x61,0x31,0x62,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+ldsetpl x21, x22, [sp]
+// CHECK: ldsetpl x21, x22, [sp] // encoding: [0xf5,0x33,0x76,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+ldsetpl x22, xzr, [sp]
+// ERROR-INVALID-OP: [[@LINE-1]]:15: error: invalid operand for instruction
+// ERROR-NO-LSE128: error: invalid operand for instruction
+ldsetpl xzr, x22, [sp]
+// ERROR-INVALID-OP: [[@LINE-1]]:10: error: invalid operand for instruction
+// ERROR-NO-LSE128: error: invalid operand for instruction
+
+
+swpp x1, x2, [x11]
+// CHECK: swpp x1, x2, [x11] // encoding: [0x61,0x81,0x22,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+swpp x21, x22, [sp]
+// CHECK: swpp x21, x22, [sp] // encoding: [0xf5,0x83,0x36,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+swppa x1, x2, [x11]
+// CHECK: swppa x1, x2, [x11] // encoding: [0x61,0x81,0xa2,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+swppa x21, x22, [sp]
+// CHECK: swppa x21, x22, [sp] // encoding: [0xf5,0x83,0xb6,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+swppal x1, x2, [x11]
+// CHECK: swppal x1, x2, [x11] // encoding: [0x61,0x81,0xe2,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+swppal x21, x22, [sp]
+// CHECK: swppal x21, x22, [sp] // encoding: [0xf5,0x83,0xf6,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+swppl x1, x2, [x11]
+// CHECK: swppl x1, x2, [x11] // encoding: [0x61,0x81,0x62,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+swppl x21, x22, [sp]
+// CHECK: swppl x21, x22, [sp] // encoding: [0xf5,0x83,0x76,0x19]
+// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128
+swppl x22, xzr, [sp]
+// ERROR-INVALID-OP: [[@LINE-1]]:15: error: invalid operand for instruction
+// ERROR-NO-LSE128: error: invalid operand for instruction
+swppl xzr, x22, [sp]
+// ERROR-INVALID-OP: [[@LINE-1]]:10: error: invalid operand for instruction
+// ERROR-NO-LSE128: error: invalid operand for instruction
+
diff --git a/llvm/test/MC/AArch64/basic-a64-instructions.s b/llvm/test/MC/AArch64/basic-a64-instructions.s
index 02e0f32ef6277..06d5a358e95e0 100644
--- a/llvm/test/MC/AArch64/basic-a64-instructions.s
+++ b/llvm/test/MC/AArch64/basic-a64-instructions.s
@@ -3939,6 +3939,33 @@ _func:
msr PMEVTYPER28_EL0, x12
msr PMEVTYPER29_EL0, x12
msr PMEVTYPER30_EL0, x12
+ msr AMAIR2_EL1, x12
+ msr AMAIR2_EL12, x12
+ msr AMAIR2_EL2, x12
+ msr AMAIR2_EL3, x12
+ msr MAIR2_EL1, x12
+ msr MAIR2_EL12, x12
+ msr MAIR2_EL2, x12
+ msr MAIR2_EL3, x12
+ msr PIRE0_EL1, x12
+ msr PIRE0_EL2, x12
+ msr PIR_EL1, x12
+ msr PIR_EL12, x12
+ msr PIR_EL2, x12
+ msr PIR_EL3, x12
+ msr S2PIR_EL2, x12
+ msr POR_EL0, x12
+ msr POR_EL1, x12
+ msr POR_EL12, x12
+ msr POR_EL2, x12
+ msr POR_EL3, x12
+ msr S2POR_EL1, x12
+ msr SCTLR2_EL1, x12
+ msr SCTLR2_EL12, x12
+ msr SCTLR2_EL2, x12
+ msr TCR2_EL1, x12
+ msr TCR2_EL12, x12
+ msr TCR2_EL2, x12
// CHECK: msr {{teecr32_el1|TEECR32_EL1}}, x12 // encoding: [0x0c,0x00,0x12,0xd5]
// CHECK: msr {{osdtrrx_el1|OSDTRRX_EL1}}, x12 // encoding: [0x4c,0x00,0x10,0xd5]
// CHECK: msr {{mdccint_el1|MDCCINT_EL1}}, x12 // encoding: [0x0c,0x02,0x10,0xd5]
@@ -4192,6 +4219,33 @@ _func:
// CHECK: msr {{pmevtyper28_el0|PMEVTYPER28_EL0}}, x12 // encoding: [0x8c,0xef,0x1b,0xd5]
// CHECK: msr {{pmevtyper29_el0|PMEVTYPER29_EL0}}, x12 // encoding: [0xac,0xef,0x1b,0xd5]
// CHECK: msr {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12 // encoding: [0xcc,0xef,0x1b,0xd5]
+// CHECK: msr {{amair2_el1|AMAIR2_EL1}}, x12 // encoding: [0x2c,0xa3,0x18,0xd5]
+// CHECK: msr {{amair2_el12|AMAIR2_EL12}}, x12 // encoding: [0x2c,0xa3,0x1d,0xd5]
+// CHECK: msr {{amair2_el2|AMAIR2_EL2}}, x12 // encoding: [0x2c,0xa3,0x1c,0xd5]
+// CHECK: msr {{amair2_el3|AMAIR2_EL3}}, x12 // encoding: [0x2c,0xa3,0x1e,0xd5]
+// CHECK: msr {{mair2_el1|MAIR2_EL1}}, x12 // encoding: [0x2c,0xa2,0x18,0xd5]
+// CHECK: msr {{mair2_el12|MAIR2_EL12}}, x12 // encoding: [0x2c,0xa2,0x1d,0xd5]
+// CHECK: msr {{mair2_el2|MAIR2_EL2}}, x12 // encoding: [0x2c,0xa1,0x1c,0xd5]
+// CHECK: msr {{mair2_el3|MAIR2_EL3}}, x12 // encoding: [0x2c,0xa1,0x1e,0xd5]
+// CHECK: msr {{pire0_el1|PIRE0_EL1}}, x12 // encoding: [0x4c,0xa2,0x18,0xd5]
+// CHECK: msr {{pire0_el2|PIRE0_EL2}}, x12 // encoding: [0x4c,0xa2,0x1c,0xd5]
+// CHECK: msr {{pir_el1|PIR_EL1}}, x12 // encoding: [0x6c,0xa2,0x18,0xd5]
+// CHECK: msr {{pir_el12|PIR_EL12}}, x12 // encoding: [0x6c,0xa2,0x1d,0xd5]
+// CHECK: msr {{pir_el2|PIR_EL2}}, x12 // encoding: [0x6c,0xa2,0x1c,0xd5]
+// CHECK: msr {{pir_el3|PIR_EL3}}, x12 // encoding: [0x6c,0xa2,0x1e,0xd5]
+// CHECK: msr {{s2pir_el2|S2PIR_EL2}}, x12 // encoding: [0xac,0xa2,0x1c,0xd5]
+// CHECK: msr {{por_el0|POR_EL0}}, x12 // encoding: [0x8c,0xa2,0x1b,0xd5]
+// CHECK: msr {{por_el1|POR_EL1}}, x12 // encoding: [0x8c,0xa2,0x18,0xd5]
+// CHECK: msr {{por_el12|POR_EL12}}, x12 // encoding: [0x8c,0xa2,0x1d,0xd5]
+// CHECK: msr {{por_el2|POR_EL2}}, x12 // encoding: [0x8c,0xa2,0x1c,0xd5]
+// CHECK: msr {{por_el3|POR_EL3}}, x12 // encoding: [0x8c,0xa2,0x1e,0xd5]
+// CHECK: msr {{s2por_el1|S2POR_EL1}}, x12 // encoding: [0xac,0xa2,0x18,0xd5]
+// CHECK: msr {{sctlr2_el1|SCTLR2_EL1}}, x12 // encoding: [0x6c,0x10,0x18,0xd5]
+// CHECK: msr {{sctlr2_el12|SCTLR2_EL12}}, x12 // encoding: [0x6c,0x10,0x1d,0xd5]
+// CHECK: msr {{sctlr2_el2|SCTLR2_EL2}}, x12 // encoding: [0x6c,0x10,0x1c,0xd5]
+// CHECK: msr {{tcr2_el1|TCR2_EL1}}, x12 // encoding: [0x6c,0x20,0x18,0xd5]
+// CHECK: msr {{tcr2_el12|TCR2_EL12}}, x12 // encoding: [0x6c,0x20,0x1d,0xd5]
+// CHECK: msr {{tcr2_el2|TCR2_EL2}}, x12 // encoding: [0x6c,0x20,0x1c,0xd5]
mrs x9, TEECR32_EL1
mrs x9, OSDTRRX_EL1
@@ -4497,6 +4551,33 @@ _func:
mrs x9, PMEVTYPER28_EL0
mrs x9, PMEVTYPER29_EL0
mrs x9, PMEVTYPER30_EL0
+ mrs x9, AMAIR2_EL1
+ mrs x9, AMAIR2_EL12
+ mrs x9, AMAIR2_EL2
+ mrs x9, AMAIR2_EL3
+ mrs x9, MAIR2_EL1
+ mrs x9, MAIR2_EL12
+ mrs x9, MAIR2_EL2
+ mrs x9, MAIR2_EL3
+ mrs x9, PIRE0_EL1
+ mrs x9, PIRE0_EL2
+ mrs x9, PIR_EL1
+ mrs x9, PIR_EL12
+ mrs x9, PIR_EL2
+ mrs x9, PIR_EL3
+ mrs x9, S2PIR_EL2
+ mrs x9, POR_EL0
+ mrs x9, POR_EL1
+ mrs x9, POR_EL12
+ mrs x9, POR_EL2
+ mrs x9, POR_EL3
+ mrs x9, S2POR_EL1
+ mrs x9, SCTLR2_EL1
+ mrs x9, SCTLR2_EL12
+ mrs x9, SCTLR2_EL2
+ mrs x9, TCR2_EL1
+ mrs x9, TCR2_EL12
+ mrs x9, TCR2_EL2
// CHECK: mrs x9, {{teecr32_el1|TEECR32_EL1}} // encoding: [0x09,0x00,0x32,0xd5]
// CHECK: mrs x9, {{osdtrrx_el1|OSDTRRX_EL1}} // encoding: [0x49,0x00,0x30,0xd5]
// CHECK: mrs x9, {{mdccsr_el0|MDCCSR_EL0}} // encoding: [0x09,0x01,0x33,0xd5]
@@ -4801,6 +4882,33 @@ _func:
// CHECK: mrs x9, {{pmevtyper28_el0|PMEVTYPER28_EL0}} // encoding: [0x89,0xef,0x3b,0xd5]
// CHECK: mrs x9, {{pmevtyper29_el0|PMEVTYPER29_EL0}} // encoding: [0xa9,0xef,0x3b,0xd5]
// CHECK: mrs x9, {{pmevtyper30_el0|PMEVTYPER30_EL0}} // encoding: [0xc9,0xef,0x3b,0xd5]
+// CHECK: mrs x9, {{amair2_el1|AMAIR2_EL1}} // encoding: [0x29,0xa3,0x38,0xd5]
+// CHECK: mrs x9, {{amair2_el12|AMAIR2_EL12}} // encoding: [0x29,0xa3,0x3d,0xd5]
+// CHECK: mrs x9, {{amair2_el2|AMAIR2_EL2}} // encoding: [0x29,0xa3,0x3c,0xd5]
+// CHECK: mrs x9, {{amair2_el3|AMAIR2_EL3}} // encoding: [0x29,0xa3,0x3e,0xd5]
+// CHECK: mrs x9, {{mair2_el1|MAIR2_EL1}} // encoding: [0x29,0xa2,0x38,0xd5]
+// CHECK: mrs x9, {{mair2_el12|MAIR2_EL12}} // encoding: [0x29,0xa2,0x3d,0xd5]
+// CHECK: mrs x9, {{mair2_el2|MAIR2_EL2}} // encoding: [0x29,0xa1,0x3c,0xd5]
+// CHECK: mrs x9, {{mair2_el3|MAIR2_EL3}} // encoding: [0x29,0xa1,0x3e,0xd5]
+// CHECK: mrs x9, {{pire0_el1|PIRE0_EL1}} // encoding: [0x49,0xa2,0x38,0xd5]
+// CHECK: mrs x9, {{pire0_el2|PIRE0_EL2}} // encoding: [0x49,0xa2,0x3c,0xd5]
+// CHECK: mrs x9, {{pir_el1|PIR_EL1}} // encoding: [0x69,0xa2,0x38,0xd5]
+// CHECK: mrs x9, {{pir_el12|PIR_EL12}} // encoding: [0x69,0xa2,0x3d,0xd5]
+// CHECK: mrs x9, {{pir_el2|PIR_EL2}} // encoding: [0x69,0xa2,0x3c,0xd5]
+// CHECK: mrs x9, {{pir_el3|PIR_EL3}} // encoding: [0x69,0xa2,0x3e,0xd5]
+// CHECK: mrs x9, {{s2pir_el2|S2PIR_EL2}} // encoding: [0xa9,0xa2,0x3c,0xd5]
+// CHECK: mrs x9, {{por_el0|POR_EL0}} // encoding: [0x89,0xa2,0x3b,0xd5]
+// CHECK: mrs x9, {{por_el1|POR_EL1}} // encoding: [0x89,0xa2,0x38,0xd5]
+// CHECK: mrs x9, {{por_el12|POR_EL12}} // encoding: [0x89,0xa2,0x3d,0xd5]
+// CHECK: mrs x9, {{por_el2|POR_EL2}} // encoding: [0x89,0xa2,0x3c,0xd5]
+// CHECK: mrs x9, {{por_el3|POR_EL3}} // encoding: [0x89,0xa2,0x3e,0xd5]
+// CHECK: mrs x9, {{s2por_el1|S2POR_EL1}} // encoding: [0xa9,0xa2,0x38,0xd5]
+// CHECK: mrs x9, {{sctlr2_el1|SCTLR2_EL1}} // encoding: [0x69,0x10,0x38,0xd5]
+// CHECK: mrs x9, {{sctlr2_el12|SCTLR2_EL12}} // encoding: [0x69,0x10,0x3d,0xd5]
+// CHECK: mrs x9, {{sctlr2_el2|SCTLR2_EL2}} // encoding: [0x69,0x10,0x3c,0xd5]
+// CHECK: mrs x9, {{tcr2_el1|TCR2_EL1}} // encoding: [0x69,0x20,0x38,0xd5]
+// CHECK: mrs x9, {{tcr2_el12|TCR2_EL12}} // encoding: [0x69,0x20,0x3d,0xd5]
+// CHECK: mrs x9, {{tcr2_el2|TCR2_EL2}} // encoding: [0x69,0x20,0x3c,0xd5]
mrs x12, s3_7_c15_c1_5
mrs x13, s3_2_c11_c15_7
diff --git a/llvm/test/MC/AArch64/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/directive-arch_extension-negative.s
index 16f3bb8598156..13588def5f8d8 100644
--- a/llvm/test/MC/AArch64/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/directive-arch_extension-negative.s
@@ -1,5 +1,6 @@
// RUN: not llvm-mc -triple aarch64 \
// RUN: -mattr=+crc,+sm4,+sha3,+sha2,+aes,+fp,+neon,+ras,+lse,+predres,+ccdp,+mte,+tlb-rmi,+pan-rwv,+ccpp,+rcpc,+ls64,+flagm,+hbc,+mops \
+// RUN: -mattr=+rcpc3,+lse128,+d128,+the \
// RUN: -filetype asm -o - %s 2>&1 | FileCheck %s
.arch_extension axp64
@@ -146,3 +147,24 @@ cpyfp [x0]!, [x1]!, x2!
cpyfp [x0]!, [x1]!, x2!
// CHECK: [[@LINE-1]]:1: error: instruction requires: mops
// CHECK-NEXT: cpyfp [x0]!, [x1]!, x2!
+
+// This needs to come before `.arch_extension nothe` as it uses an instruction
+// that requires both the and d128
+sysp #0, c2, c0, #0, x0, x1
+rcwcasp x0, x1, x6, x7, [x4]
+// CHECK-NOT: [[@LINE-2]]:1: error: instruction requires: d128
+// CHECK-NOT: [[@LINE-2]]:1: error: instruction requires: d128
+.arch_extension nod128
+sysp #0, c2, c0, #0, x0, x1
+rcwcasp x0, x1, x6, x7, [x4]
+// CHECK: [[@LINE-2]]:1: error: instruction requires: d128
+// CHECK-NEXT: sysp #0, c2, c0, #0, x0, x1
+// CHECK: [[@LINE-3]]:1: error: instruction requires: d128
+// CHECK-NEXT: rcwcasp x0, x1, x6, x7, [x4]
+
+rcwswp x0, x1, [x2]
+// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: the
+.arch_extension nothe
+rcwswp x0, x1, [x2]
+// CHECK: [[@LINE-1]]:1: error: instruction requires: the
+// CHECK-NEXT: rcwswp x0, x1, [x2]
diff --git a/llvm/test/MC/AArch64/directive-arch_extension.s b/llvm/test/MC/AArch64/directive-arch_extension.s
index 9274e80047a8b..101c48b689380 100644
--- a/llvm/test/MC/AArch64/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/directive-arch_extension.s
@@ -92,3 +92,15 @@ lbl:
.arch_extension mops
cpyfp [x0]!, [x1]!, x2!
// CHECK: cpyfp [x0]!, [x1]!, x2!
+
+.arch_extension the
+rcwswp x0, x1, [x2]
+// CHECK: rcwswp x0, x1, [x2]
+
+// This needs to come after `.arch_extension the` as it uses an instruction that
+// requires both the and d128
+.arch_extension d128
+sysp #0, c2, c0, #0, x0, x1
+rcwcasp x0, x1, x6, x7, [x4]
+// CHECK: sysp #0, c2, c0, #0, x0, x1
+// CHECK: rcwcasp x0, x1, x6, x7, [x4]
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.9a-the.txt b/llvm/test/MC/Disassembler/AArch64/armv8.9a-the.txt
new file mode 100644
index 0000000000000..f3b313a36487b
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.9a-the.txt
@@ -0,0 +1,482 @@
+# RUN: llvm-mc -triple=aarch64 -mattr=+the -mattr=+d128 -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.9a -mattr=+the -mattr=+d128 -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v9.4a -mattr=+the -mattr=+d128 -disassemble %s | FileCheck %s
+# RUN: not llvm-mc -triple=aarch64 -disassemble %s 2>&1 | FileCheck %s --check-prefix=ERROR-NO-THE
+# RUN: not llvm-mc -triple=aarch64 -mattr=+v8.9a -disassemble %s 2>&1 | FileCheck %s --check-prefix=ERROR-NO-THE
+# RUN: not llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble %s 2>&1 | FileCheck %s --check-prefix=ERROR-NO-THE
+# RUN: not llvm-mc -triple=aarch64 -mattr=+the -disassemble %s 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128
+# RUN: not llvm-mc -triple=aarch64 -mattr=+v8.9a -mattr=+the -disassemble %s 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128
+# RUN: not llvm-mc -triple=aarch64 -mattr=+v9.4a -mattr=+the -disassemble %s 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128
+
+[0xc3,0xd0,0x38,0xd5]
+# CHECK: mrs x3, RCWMASK_EL1
+[0xc1,0xd0,0x18,0xd5]
+# CHECK: msr RCWMASK_EL1, x1
+[0x63,0xd0,0x38,0xd5]
+# CHECK: mrs x3, RCWSMASK_EL1
+[0x61,0xd0,0x18,0xd5]
+# CHECK: msr RCWSMASK_EL1, x1
+
+[0x81,0x08,0x20,0x19]
+# CHECK: rcwcas x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0x08,0xa0,0x19]
+# CHECK: rcwcasa x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0x08,0xe0,0x19]
+# CHECK: rcwcasal x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0x08,0x60,0x19]
+# CHECK: rcwcasl x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0x0b,0x23,0x19]
+# CHECK: rcwcas x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0x0b,0xa3,0x19]
+# CHECK: rcwcasa x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0x0b,0xe3,0x19]
+# CHECK: rcwcasal x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0x0b,0x63,0x19]
+# CHECK: rcwcasl x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x81,0x08,0x20,0x59]
+# CHECK: rcwscas x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0x08,0xa0,0x59]
+# CHECK: rcwscasa x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0x08,0xe0,0x59]
+# CHECK: rcwscasal x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0x08,0x60,0x59]
+# CHECK: rcwscasl x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0x0b,0x23,0x59]
+# CHECK: rcwscas x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0x0b,0xa3,0x59]
+# CHECK: rcwscasa x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0x0b,0xe3,0x59]
+# CHECK: rcwscasal x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0x0b,0x63,0x59]
+# CHECK: rcwscasl x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x86,0x0c,0x20,0x19]
+# CHECK: rcwcasp x0, x1, x6, x7, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x86,0x0c,0xa0,0x19]
+# CHECK: rcwcaspa x0, x1, x6, x7, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x86,0x0c,0xe0,0x19]
+# CHECK: rcwcaspal x0, x1, x6, x7, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x86,0x0c,0x60,0x19]
+# CHECK: rcwcaspl x0, x1, x6, x7, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe6,0x0f,0x24,0x19]
+# CHECK: rcwcasp x4, x5, x6, x7, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe6,0x0f,0xa4,0x19]
+# CHECK: rcwcaspa x4, x5, x6, x7, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe6,0x0f,0xe4,0x19]
+# CHECK: rcwcaspal x4, x5, x6, x7, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe6,0x0f,0x64,0x19]
+# CHECK: rcwcaspl x4, x5, x6, x7, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+
+[0x86,0x0c,0x20,0x59]
+# CHECK: rcwscasp x0, x1, x6, x7, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x86,0x0c,0xa0,0x59]
+# CHECK: rcwscaspa x0, x1, x6, x7, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x86,0x0c,0xe0,0x59]
+# CHECK: rcwscaspal x0, x1, x6, x7, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x86,0x0c,0x60,0x59]
+# CHECK: rcwscaspl x0, x1, x6, x7, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe6,0x0f,0x24,0x59]
+# CHECK: rcwscasp x4, x5, x6, x7, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe6,0x0f,0xa4,0x59]
+# CHECK: rcwscaspa x4, x5, x6, x7, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe6,0x0f,0xe4,0x59]
+# CHECK: rcwscaspal x4, x5, x6, x7, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe6,0x0f,0x64,0x59]
+# CHECK: rcwscaspl x4, x5, x6, x7, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+
+[0x81,0x90,0x20,0x38]
+# CHECK: rcwclr x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0x90,0xa0,0x38]
+# CHECK: rcwclra x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0x90,0xe0,0x38]
+# CHECK: rcwclral x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0x90,0x60,0x38]
+# CHECK: rcwclrl x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0x93,0x23,0x38]
+# CHECK: rcwclr x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0x93,0xa3,0x38]
+# CHECK: rcwclra x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0x93,0xe3,0x38]
+# CHECK: rcwclral x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0x93,0x63,0x38]
+# CHECK: rcwclrl x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x81,0x90,0x20,0x78]
+# CHECK: rcwsclr x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0x90,0xa0,0x78]
+# CHECK: rcwsclra x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0x90,0xe0,0x78]
+# CHECK: rcwsclral x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0x90,0x60,0x78]
+# CHECK: rcwsclrl x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0x93,0x23,0x78]
+# CHECK: rcwsclr x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0x93,0xa3,0x78]
+# CHECK: rcwsclra x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0x93,0xe3,0x78]
+# CHECK: rcwsclral x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0x93,0x63,0x78]
+# CHECK: rcwsclrl x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x81,0x90,0x20,0x19]
+# CHECK: rcwclrp x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0x90,0xa0,0x19]
+# CHECK: rcwclrpa x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0x90,0xe0,0x19]
+# CHECK: rcwclrpal x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0x90,0x60,0x19]
+# CHECK: rcwclrpl x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0x93,0x23,0x19]
+# CHECK: rcwclrp x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0x93,0xa3,0x19]
+# CHECK: rcwclrpa x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0x93,0xe3,0x19]
+# CHECK: rcwclrpal x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0x93,0x63,0x19]
+# CHECK: rcwclrpl x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+
+[0x81,0x90,0x20,0x59]
+# CHECK: rcwsclrp x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0x90,0xa0,0x59]
+# CHECK: rcwsclrpa x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0x90,0xe0,0x59]
+# CHECK: rcwsclrpal x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0x90,0x60,0x59]
+# CHECK: rcwsclrpl x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0x93,0x23,0x59]
+# CHECK: rcwsclrp x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0x93,0xa3,0x59]
+# CHECK: rcwsclrpa x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0x93,0xe3,0x59]
+# CHECK: rcwsclrpal x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0x93,0x63,0x59]
+# CHECK: rcwsclrpl x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+
+[0x81,0xb0,0x20,0x38]
+# CHECK: rcwset x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0xb0,0xa0,0x38]
+# CHECK: rcwseta x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0xb0,0xe0,0x38]
+# CHECK: rcwsetal x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0xb0,0x60,0x38]
+# CHECK: rcwsetl x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0xb3,0x23,0x38]
+# CHECK: rcwset x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0xb3,0xa3,0x38]
+# CHECK: rcwseta x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0xb3,0xe3,0x38]
+# CHECK: rcwsetal x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0xb3,0x63,0x38]
+# CHECK: rcwsetl x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x81,0xb0,0x20,0x78]
+# CHECK: rcwsset x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0xb0,0xa0,0x78]
+# CHECK: rcwsseta x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0xb0,0xe0,0x78]
+# CHECK: rcwssetal x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0xb0,0x60,0x78]
+# CHECK: rcwssetl x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0xb3,0x23,0x78]
+# CHECK: rcwsset x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0xb3,0xa3,0x78]
+# CHECK: rcwsseta x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0xb3,0xe3,0x78]
+# CHECK: rcwssetal x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0xb3,0x63,0x78]
+# CHECK: rcwssetl x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x81,0xb0,0x20,0x19]
+# CHECK: rcwsetp x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0xb0,0xa0,0x19]
+# CHECK: rcwsetpa x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0xb0,0xe0,0x19]
+# CHECK: rcwsetpal x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0xb0,0x60,0x19]
+# CHECK: rcwsetpl x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0xb3,0x23,0x19]
+# CHECK: rcwsetp x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0xb3,0xa3,0x19]
+# CHECK: rcwsetpa x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0xb3,0xe3,0x19]
+# CHECK: rcwsetpal x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0xb3,0x63,0x19]
+# CHECK: rcwsetpl x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+
+[0x81,0xb0,0x20,0x59]
+# CHECK: rcwssetp x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0xb0,0xa0,0x59]
+# CHECK: rcwssetpa x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0xb0,0xe0,0x59]
+# CHECK: rcwssetpal x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0xb0,0x60,0x59]
+# CHECK: rcwssetpl x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0xb3,0x23,0x59]
+# CHECK: rcwssetp x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0xb3,0xa3,0x59]
+# CHECK: rcwssetpa x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0xb3,0xe3,0x59]
+# CHECK: rcwssetpal x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0xb3,0x63,0x59]
+# CHECK: rcwssetpl x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+
+[0x81,0xa0,0x20,0x38]
+# CHECK: rcwswp x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0xa0,0xa0,0x38]
+# CHECK: rcwswpa x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0xa0,0xe0,0x38]
+# CHECK: rcwswpal x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0xa0,0x60,0x38]
+# CHECK: rcwswpl x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0xa3,0x23,0x38]
+# CHECK: rcwswp x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0xa3,0xa3,0x38]
+# CHECK: rcwswpa x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0xa3,0xe3,0x38]
+# CHECK: rcwswpal x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0xa3,0x63,0x38]
+# CHECK: rcwswpl x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x81,0xa0,0x20,0x78]
+# CHECK: rcwsswp x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0xa0,0xa0,0x78]
+# CHECK: rcwsswpa x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0xa0,0xe0,0x78]
+# CHECK: rcwsswpal x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0x81,0xa0,0x60,0x78]
+# CHECK: rcwsswpl x0, x1, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0xa3,0x23,0x78]
+# CHECK: rcwsswp x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0xa3,0xa3,0x78]
+# CHECK: rcwsswpa x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0xa3,0xe3,0x78]
+# CHECK: rcwsswpal x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+[0xe5,0xa3,0x63,0x78]
+# CHECK: rcwsswpl x3, x5, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x81,0xa0,0x20,0x19]
+# CHECK: rcwswpp x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0xa0,0xa0,0x19]
+# CHECK: rcwswppa x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0xa0,0xe0,0x19]
+# CHECK: rcwswppal x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0xa0,0x60,0x19]
+# CHECK: rcwswppl x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0xa3,0x23,0x19]
+# CHECK: rcwswpp x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0xa3,0xa3,0x19]
+# CHECK: rcwswppa x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0xa3,0xe3,0x19]
+# CHECK: rcwswppal x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0xa3,0x63,0x19]
+# CHECK: rcwswppl x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+
+[0x81,0xa0,0x20,0x59]
+# CHECK: rcwsswpp x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0xa0,0xa0,0x59]
+# CHECK: rcwsswppa x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0xa0,0xe0,0x59]
+# CHECK: rcwsswppal x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0x81,0xa0,0x60,0x59]
+# CHECK: rcwsswppl x1, x0, [x4]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0xa3,0x23,0x59]
+# CHECK: rcwsswpp x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0xa3,0xa3,0x59]
+# CHECK: rcwsswppa x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0xa3,0xe3,0x59]
+# CHECK: rcwsswppal x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
+[0xe5,0xa3,0x63,0x59]
+# CHECK: rcwsswppl x5, x3, [sp]
+# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding
+# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9-sysp.txt b/llvm/test/MC/Disassembler/AArch64/armv9-sysp.txt
new file mode 100644
index 0000000000000..2bbdef4d5518e
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv9-sysp.txt
@@ -0,0 +1,562 @@
+# RUN: llvm-mc -triple aarch64 --disassemble -mattr=+d128,+tlb-rmi,+xs %s -o - 2> %t | FileCheck %s
+# RUN: FileCheck %s --check-prefix=INVALID --input-file=%t
+
+# RUN: llvm-mc -triple aarch64 --disassemble %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128
+
+0x00 0x20 0x48 0xd5
+0x20 0x20 0x48 0xd5
+0x00 0x74 0x48 0xd5
+0x60 0xd0 0x48 0xd5
+0xc0 0xd0 0x48 0xd5
+0x00 0x20 0x4c 0xd5
+0x20 0x20 0x4c 0xd5
+0x00 0x21 0x4c 0xd5
+0x00 0x20 0x48 0xd5
+0x20 0x20 0x48 0xd5
+0x00 0x74 0x48 0xd5
+0x60 0xd0 0x48 0xd5
+0xc0 0xd0 0x48 0xd5
+0x00 0x20 0x4c 0xd5
+0x20 0x20 0x4c 0xd5
+0x00 0x21 0x4c 0xd5
+0x00 0x20 0x48 0xd5
+0x02 0x20 0x48 0xd5
+0x04 0x20 0x48 0xd5
+0x06 0x20 0x48 0xd5
+0x08 0x20 0x48 0xd5
+0x0a 0x20 0x48 0xd5
+0x0c 0x20 0x48 0xd5
+0x0e 0x20 0x48 0xd5
+0x10 0x20 0x48 0xd5
+0x12 0x20 0x48 0xd5
+0x14 0x20 0x48 0xd5
+0x16 0x20 0x48 0xd5
+0x18 0x20 0x48 0xd5
+0x1a 0x20 0x48 0xd5
+0x1c 0x20 0x48 0xd5
+0x1e 0x20 0x48 0xd5
+0x1f 0x20 0x48 0xd5
+
+# CHECK: sysp #0, c2, c0, #0, x0, x1
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #1, x0, x1
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c7, c4, #0, x0, x1
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c13, c0, #3, x0, x1
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c13, c0, #6, x0, x1
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #4, c2, c0, #0, x0, x1
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #4, c2, c0, #1, x0, x1
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #4, c2, c1, #0, x0, x1
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0, x0, x1
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #1, x0, x1
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c7, c4, #0, x0, x1
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c13, c0, #3, x0, x1
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c13, c0, #6, x0, x1
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #4, c2, c0, #0, x0, x1
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #4, c2, c0, #1, x0, x1
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #4, c2, c1, #0, x0, x1
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0, x0, x1
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0, x2, x3
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0, x4, x5
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0, x6, x7
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0, x10, x11
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0, x12, x13
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0, x14, x15
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0, x16, x17
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0, x20, x21
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0, x22, x23
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0, x24, x25
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0, x26, x27
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0, x28, x29
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0, x30, xzr
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK-NEXT: sysp #0, c2, c0, #0
+# ERROR-NO-D128: warning: invalid instruction encoding
+
+
+
+0x01 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x1, x2
+# INVALID: warning: invalid instruction encoding
+# INVALID-NEXT: 0x01 0x20 0x48 0xd5
+
+0x03 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x3, x4
+# INVALID: warning: invalid instruction encoding
+# INVALID-NEXT: 0x03 0x20 0x48 0xd5
+
+0x05 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x5, x6
+# INVALID: warning: invalid instruction encoding
+# INVALID-NEXT: 0x05 0x20 0x48 0xd5
+
+0x07 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x7, x8
+# INVALID: warning: invalid instruction encoding
+# INVALID-NEXT: 0x07 0x20 0x48 0xd5
+
+0x09 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x9, x10
+# INVALID: warning: invalid instruction encoding
+# INVALID-NEXT: 0x09 0x20 0x48 0xd5
+
+0x0b 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x11, x12
+# INVALID: warning: invalid instruction encoding
+# INVALID-NEXT: 0x0b 0x20 0x48 0xd5
+
+0x0d 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x13, x14
+# INVALID: warning: invalid instruction encoding
+# INVALID-NEXT: 0x0d 0x20 0x48 0xd5
+
+0x0f 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x15, x16
+# INVALID: warning: invalid instruction encoding
+# INVALID-NEXT: 0x0f 0x20 0x48 0xd5
+
+0x11 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x17, x18
+# INVALID: warning: invalid instruction encoding
+# INVALID-NEXT: 0x11 0x20 0x48 0xd5
+
+0x13 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x19, x20
+# INVALID: warning: invalid instruction encoding
+# INVALID-NEXT: 0x13 0x20 0x48 0xd5
+
+0x15 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x21, x22
+# INVALID: warning: invalid instruction encoding
+# INVALID-NEXT: 0x15 0x20 0x48 0xd5
+
+0x17 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x23, x24
+# INVALID: warning: invalid instruction encoding
+# INVALID-NEXT: 0x17 0x20 0x48 0xd5
+
+0x19 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x25, x26
+# INVALID: warning: invalid instruction encoding
+# INVALID-NEXT: 0x19 0x20 0x48 0xd5
+
+0x1b 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x27, x28
+# INVALID: warning: invalid instruction encoding
+# INVALID-NEXT: 0x1b 0x20 0x48 0xd5
+
+0x1d 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x29, x30
+# INVALID: warning: invalid instruction encoding
+# INVALID-NEXT: 0x1d 0x20 0x48 0xd5
+
+0x24 0x80 0x4c 0xd5
+# CHECK: tlbip ipas2e1is, x4, x5
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x24 0x90 0x4c 0xd5
+# CHECK: tlbip ipas2e1isnxs, x4, x5
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x24 0x84 0x4c 0xd5
+# CHECK: tlbip ipas2e1, x4, x5
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x24 0x94 0x4c 0xd5
+# CHECK: tlbip ipas2e1nxs, x4, x5
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x04 0x84 0x4c 0xd5
+# CHECK: tlbip ipas2e1os, x4, x5
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x04 0x94 0x4c 0xd5
+# CHECK: tlbip ipas2e1osnxs, x4, x5
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xa4 0x84 0x4c 0xd5
+# CHECK: tlbip ipas2le1, x4, x5
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xa4 0x94 0x4c 0xd5
+# CHECK: tlbip ipas2le1nxs, x4, x5
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xa4 0x80 0x4c 0xd5
+# CHECK: tlbip ipas2le1is, x4, x5
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xa4 0x90 0x4c 0xd5
+# CHECK: tlbip ipas2le1isnxs, x4, x5
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x84 0x84 0x4c 0xd5
+# CHECK: tlbip ipas2le1os, x4, x5
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x84 0x94 0x4c 0xd5
+# CHECK: tlbip ipas2le1osnxs, x4, x5
+# ERROR-NO-D128: warning: invalid instruction encoding
+
+
+0x28 0x83 0x48 0xd5
+# CHECK: tlbip vae1is, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x28 0x93 0x48 0xd5
+# CHECK: tlbip vae1isnxs, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x28 0x87 0x48 0xd5
+# CHECK: tlbip vae1, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x28 0x97 0x48 0xd5
+# CHECK: tlbip vae1nxs, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x28 0x83 0x48 0xd5
+# CHECK: tlbip vae1is, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x28 0x93 0x48 0xd5
+# CHECK: tlbip vae1isnxs, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x28 0x81 0x48 0xd5
+# CHECK: tlbip vae1os, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x28 0x91 0x48 0xd5
+# CHECK: tlbip vae1osnxs, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xa8 0x87 0x48 0xd5
+# CHECK: tlbip vale1, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xa8 0x97 0x48 0xd5
+# CHECK: tlbip vale1nxs, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xa8 0x83 0x48 0xd5
+# CHECK: tlbip vale1is, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xa8 0x93 0x48 0xd5
+# CHECK: tlbip vale1isnxs, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xa8 0x81 0x48 0xd5
+# CHECK: tlbip vale1os, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xa8 0x91 0x48 0xd5
+# CHECK: tlbip vale1osnxs, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x68 0x87 0x48 0xd5
+# CHECK: tlbip vaae1, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x68 0x97 0x48 0xd5
+# CHECK: tlbip vaae1nxs, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x68 0x83 0x48 0xd5
+# CHECK: tlbip vaae1is, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x68 0x93 0x48 0xd5
+# CHECK: tlbip vaae1isnxs, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x68 0x81 0x48 0xd5
+# CHECK: tlbip vaae1os, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x68 0x91 0x48 0xd5
+# CHECK: tlbip vaae1osnxs, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xe8 0x87 0x48 0xd5
+# CHECK: tlbip vaale1, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xe8 0x97 0x48 0xd5
+# CHECK: tlbip vaale1nxs, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xe8 0x83 0x48 0xd5
+# CHECK: tlbip vaale1is, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xe8 0x93 0x48 0xd5
+# CHECK: tlbip vaale1isnxs, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xe8 0x81 0x48 0xd5
+# CHECK: tlbip vaale1os, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xe8 0x91 0x48 0xd5
+# CHECK: tlbip vaale1osnxs, x8, x9
+# ERROR-NO-D128: warning: invalid instruction encoding
+
+0x2e 0x87 0x4c 0xd5
+# CHECK: tlbip vae2, x14, x15
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x2e 0x97 0x4c 0xd5
+# CHECK: tlbip vae2nxs, x14, x15
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x2e 0x83 0x4c 0xd5
+# CHECK: tlbip vae2is, x14, x15
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x2e 0x93 0x4c 0xd5
+# CHECK: tlbip vae2isnxs, x14, x15
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x2e 0x81 0x4c 0xd5
+# CHECK: tlbip vae2os, x14, x15
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x2e 0x91 0x4c 0xd5
+# CHECK: tlbip vae2osnxs, x14, x15
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xae 0x87 0x4c 0xd5
+# CHECK: tlbip vale2, x14, x15
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xae 0x97 0x4c 0xd5
+# CHECK: tlbip vale2nxs, x14, x15
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xae 0x83 0x4c 0xd5
+# CHECK: tlbip vale2is, x14, x15
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xae 0x93 0x4c 0xd5
+# CHECK: tlbip vale2isnxs, x14, x15
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xae 0x81 0x4c 0xd5
+# CHECK: tlbip vale2os, x14, x15
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xae 0x91 0x4c 0xd5
+# CHECK: tlbip vale2osnxs, x14, x15
+# ERROR-NO-D128: warning: invalid instruction encoding
+
+0x38 0x87 0x4e 0xd5
+# CHECK: tlbip vae3, x24, x25
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x38 0x97 0x4e 0xd5
+# CHECK: tlbip vae3nxs, x24, x25
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x38 0x83 0x4e 0xd5
+# CHECK: tlbip vae3is, x24, x25
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x38 0x93 0x4e 0xd5
+# CHECK: tlbip vae3isnxs, x24, x25
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x38 0x81 0x4e 0xd5
+# CHECK: tlbip vae3os, x24, x25
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x38 0x91 0x4e 0xd5
+# CHECK: tlbip vae3osnxs, x24, x25
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xb8 0x87 0x4e 0xd5
+# CHECK: tlbip vale3, x24, x25
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xb8 0x97 0x4e 0xd5
+# CHECK: tlbip vale3nxs, x24, x25
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xb8 0x83 0x4e 0xd5
+# CHECK: tlbip vale3is, x24, x25
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xb8 0x93 0x4e 0xd5
+# CHECK: tlbip vale3isnxs, x24, x25
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xb8 0x81 0x4e 0xd5
+# CHECK: tlbip vale3os, x24, x25
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xb8 0x91 0x4e 0xd5
+# CHECK: tlbip vale3osnxs, x24, x25
+# ERROR-NO-D128: warning: invalid instruction encoding
+
+
+0x32 0x86 0x48 0xd5
+# CHECK: tlbip rvae1, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x32 0x96 0x48 0xd5
+# CHECK: tlbip rvae1nxs, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x32 0x86 0x48 0xd5
+# CHECK: tlbip rvae1, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x32 0x96 0x48 0xd5
+# CHECK: tlbip rvae1nxs, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x32 0x82 0x48 0xd5
+# CHECK: tlbip rvae1is, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x32 0x92 0x48 0xd5
+# CHECK: tlbip rvae1isnxs, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x32 0x85 0x48 0xd5
+# CHECK: tlbip rvae1os, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x32 0x95 0x48 0xd5
+# CHECK: tlbip rvae1osnxs, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x72 0x86 0x48 0xd5
+# CHECK: tlbip rvaae1, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x72 0x96 0x48 0xd5
+# CHECK: tlbip rvaae1nxs, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x72 0x82 0x48 0xd5
+# CHECK: tlbip rvaae1is, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x72 0x92 0x48 0xd5
+# CHECK: tlbip rvaae1isnxs, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x72 0x85 0x48 0xd5
+# CHECK: tlbip rvaae1os, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x72 0x95 0x48 0xd5
+# CHECK: tlbip rvaae1osnxs, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xb2 0x86 0x48 0xd5
+# CHECK: tlbip rvale1, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xb2 0x96 0x48 0xd5
+# CHECK: tlbip rvale1nxs, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xb2 0x82 0x48 0xd5
+# CHECK: tlbip rvale1is, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xb2 0x92 0x48 0xd5
+# CHECK: tlbip rvale1isnxs, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xb2 0x85 0x48 0xd5
+# CHECK: tlbip rvale1os, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xb2 0x95 0x48 0xd5
+# CHECK: tlbip rvale1osnxs, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xf2 0x86 0x48 0xd5
+# CHECK: tlbip rvaale1, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xf2 0x96 0x48 0xd5
+# CHECK: tlbip rvaale1nxs, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xf2 0x82 0x48 0xd5
+# CHECK: tlbip rvaale1is, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xf2 0x92 0x48 0xd5
+# CHECK: tlbip rvaale1isnxs, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xf2 0x85 0x48 0xd5
+# CHECK: tlbip rvaale1os, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xf2 0x95 0x48 0xd5
+# CHECK: tlbip rvaale1osnxs, x18, x19
+# ERROR-NO-D128: warning: invalid instruction encoding
+
+0x3c 0x86 0x4c 0xd5
+# CHECK: tlbip rvae2, x28, x29
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x3c 0x96 0x4c 0xd5
+# CHECK: tlbip rvae2nxs, x28, x29
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x3c 0x82 0x4c 0xd5
+# CHECK: tlbip rvae2is, x28, x29
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x3c 0x92 0x4c 0xd5
+# CHECK: tlbip rvae2isnxs, x28, x29
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x3c 0x85 0x4c 0xd5
+# CHECK: tlbip rvae2os, x28, x29
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x3c 0x95 0x4c 0xd5
+# CHECK: tlbip rvae2osnxs, x28, x29
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xbc 0x86 0x4c 0xd5
+# CHECK: tlbip rvale2, x28, x29
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xbc 0x96 0x4c 0xd5
+# CHECK: tlbip rvale2nxs, x28, x29
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xbc 0x82 0x4c 0xd5
+# CHECK: tlbip rvale2is, x28, x29
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xbc 0x92 0x4c 0xd5
+# CHECK: tlbip rvale2isnxs, x28, x29
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xbc 0x85 0x4c 0xd5
+# CHECK: tlbip rvale2os, x28, x29
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xbc 0x95 0x4c 0xd5
+# CHECK: tlbip rvale2osnxs, x28, x29
+# ERROR-NO-D128: warning: invalid instruction encoding
+
+0x2a 0x86 0x4e 0xd5
+# CHECK: tlbip rvae3, x10, x11
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x2a 0x96 0x4e 0xd5
+# CHECK: tlbip rvae3nxs, x10, x11
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x2a 0x82 0x4e 0xd5
+# CHECK: tlbip rvae3is, x10, x11
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x2a 0x92 0x4e 0xd5
+# CHECK: tlbip rvae3isnxs, x10, x11
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x2a 0x85 0x4e 0xd5
+# CHECK: tlbip rvae3os, x10, x11
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x2a 0x95 0x4e 0xd5
+# CHECK: tlbip rvae3osnxs, x10, x11
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xaa 0x86 0x4e 0xd5
+# CHECK: tlbip rvale3, x10, x11
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xaa 0x96 0x4e 0xd5
+# CHECK: tlbip rvale3nxs, x10, x11
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xaa 0x82 0x4e 0xd5
+# CHECK: tlbip rvale3is, x10, x11
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xaa 0x92 0x4e 0xd5
+# CHECK: tlbip rvale3isnxs, x10, x11
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xaa 0x85 0x4e 0xd5
+# CHECK: tlbip rvale3os, x10, x11
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xaa 0x95 0x4e 0xd5
+# CHECK: tlbip rvale3osnxs, x10, x11
+# ERROR-NO-D128: warning: invalid instruction encoding
+
+
+0x54 0x80 0x4c 0xd5
+# CHECK: tlbip ripas2e1is, x20, x21
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x54 0x90 0x4c 0xd5
+# CHECK: tlbip ripas2e1isnxs, x20, x21
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x54 0x84 0x4c 0xd5
+# CHECK: tlbip ripas2e1, x20, x21
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x54 0x94 0x4c 0xd5
+# CHECK: tlbip ripas2e1nxs, x20, x21
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x54 0x80 0x4c 0xd5
+# CHECK: tlbip ripas2e1is, x20, x21
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x54 0x90 0x4c 0xd5
+# CHECK: tlbip ripas2e1isnxs, x20, x21
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x74 0x84 0x4c 0xd5
+# CHECK: tlbip ripas2e1os, x20, x21
+# ERROR-NO-D128: warning: invalid instruction encoding
+0x74 0x94 0x4c 0xd5
+# CHECK: tlbip ripas2e1osnxs, x20, x21
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xd4 0x84 0x4c 0xd5
+# CHECK: tlbip ripas2le1, x20, x21
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xd4 0x94 0x4c 0xd5
+# CHECK: tlbip ripas2le1nxs, x20, x21
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xd4 0x80 0x4c 0xd5
+# CHECK: tlbip ripas2le1is, x20, x21
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xd4 0x90 0x4c 0xd5
+# CHECK: tlbip ripas2le1isnxs, x20, x21
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xf4 0x84 0x4c 0xd5
+# CHECK: tlbip ripas2le1os, x20, x21
+# ERROR-NO-D128: warning: invalid instruction encoding
+0xf4 0x94 0x4c 0xd5
+# CHECK: tlbip ripas2le1osnxs, x20, x21
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK: tlbip ripas2le1os, xzr, xzr
+0xff 0x84 0x4c 0xd5
+# ERROR-NO-D128: warning: invalid instruction encoding
+# CHECK: tlbip ripas2le1osnxs, xzr, xzr
+0xff 0x94 0x4c 0xd5
+# ERROR-NO-D128: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9-sysreg128.txt b/llvm/test/MC/Disassembler/AArch64/armv9-sysreg128.txt
new file mode 100644
index 0000000000000..4ab37a0200738
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv9-sysreg128.txt
@@ -0,0 +1,147 @@
+# RUN: llvm-mc -triple aarch64 -mattr=+d128 --disassemble -show-encoding %s -o - | FileCheck %s --check-prefix=WITHOUT
+# RUN: llvm-mc -triple aarch64 -mattr=+d128,+the,+el2vmsa,+vh --disassemble -show-encoding %s -o - | FileCheck %s --check-prefix=W_FEATS
+
+# RUN: llvm-mc -triple aarch64 --disassemble -show-encoding %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128
+
+0x00,0x20,0x78,0xd5
+0x20,0x20,0x78,0xd5
+0x00,0x74,0x78,0xd5
+0x60,0xd0,0x78,0xd5
+0xc0,0xd0,0x78,0xd5
+0x00,0x20,0x7c,0xd5
+0x20,0x20,0x7c,0xd5
+0x00,0x21,0x7c,0xd5
+0x00,0x21,0x7c,0xd5
+0x02,0x21,0x7c,0xd5
+0x04,0x21,0x7c,0xd5
+0x06,0x21,0x7c,0xd5
+0x08,0x21,0x7c,0xd5
+0x0a,0x21,0x7c,0xd5
+0x0c,0x21,0x7c,0xd5
+0x0e,0x21,0x7c,0xd5
+0x10,0x21,0x7c,0xd5
+0x12,0x21,0x7c,0xd5
+0x14,0x21,0x7c,0xd5
+0x16,0x21,0x7c,0xd5
+0x18,0x21,0x7c,0xd5
+0x1a,0x21,0x7c,0xd5
+
+# WITHOUT: mrrs x0, x1, TTBR0_EL1 // encoding: [0x00,0x20,0x78,0xd5]
+# WITHOUT: mrrs x0, x1, TTBR1_EL1 // encoding: [0x20,0x20,0x78,0xd5]
+# WITHOUT: mrrs x0, x1, PAR_EL1 // encoding: [0x00,0x74,0x78,0xd5]
+# WITHOUT: mrrs x0, x1, S3_0_C13_C0_3 // encoding: [0x60,0xd0,0x78,0xd5]
+# WITHOUT: mrrs x0, x1, S3_0_C13_C0_6 // encoding: [0xc0,0xd0,0x78,0xd5]
+# WITHOUT: mrrs x0, x1, S3_4_C2_C0_0 // encoding: [0x00,0x20,0x7c,0xd5]
+# WITHOUT: mrrs x0, x1, S3_4_C2_C0_1 // encoding: [0x20,0x20,0x7c,0xd5]
+# WITHOUT: mrrs x0, x1, S3_4_C2_C1_0 // encoding: [0x00,0x21,0x7c,0xd5]
+# WITHOUT: mrrs x0, x1, S3_4_C2_C1_0 // encoding: [0x00,0x21,0x7c,0xd5]
+# WITHOUT: mrrs x2, x3, S3_4_C2_C1_0 // encoding: [0x02,0x21,0x7c,0xd5]
+# WITHOUT: mrrs x4, x5, S3_4_C2_C1_0 // encoding: [0x04,0x21,0x7c,0xd5]
+# WITHOUT: mrrs x6, x7, S3_4_C2_C1_0 // encoding: [0x06,0x21,0x7c,0xd5]
+# WITHOUT: mrrs x8, x9, S3_4_C2_C1_0 // encoding: [0x08,0x21,0x7c,0xd5]
+# WITHOUT: mrrs x10, x11, S3_4_C2_C1_0 // encoding: [0x0a,0x21,0x7c,0xd5]
+# WITHOUT: mrrs x12, x13, S3_4_C2_C1_0 // encoding: [0x0c,0x21,0x7c,0xd5]
+# WITHOUT: mrrs x14, x15, S3_4_C2_C1_0 // encoding: [0x0e,0x21,0x7c,0xd5]
+# WITHOUT: mrrs x16, x17, S3_4_C2_C1_0 // encoding: [0x10,0x21,0x7c,0xd5]
+# WITHOUT: mrrs x18, x19, S3_4_C2_C1_0 // encoding: [0x12,0x21,0x7c,0xd5]
+# WITHOUT: mrrs x20, x21, S3_4_C2_C1_0 // encoding: [0x14,0x21,0x7c,0xd5]
+# WITHOUT: mrrs x22, x23, S3_4_C2_C1_0 // encoding: [0x16,0x21,0x7c,0xd5]
+# WITHOUT: mrrs x24, x25, S3_4_C2_C1_0 // encoding: [0x18,0x21,0x7c,0xd5]
+# WITHOUT: mrrs x26, x27, S3_4_C2_C1_0 // encoding: [0x1a,0x21,0x7c,0xd5]
+
+# W_FEATS: mrrs x0, x1, TTBR0_EL1 // encoding: [0x00,0x20,0x78,0xd5]
+# W_FEATS: mrrs x0, x1, TTBR1_EL1 // encoding: [0x20,0x20,0x78,0xd5]
+# W_FEATS: mrrs x0, x1, PAR_EL1 // encoding: [0x00,0x74,0x78,0xd5]
+# W_FEATS: mrrs x0, x1, RCWSMASK_EL1 // encoding: [0x60,0xd0,0x78,0xd5]
+# W_FEATS: mrrs x0, x1, RCWMASK_EL1 // encoding: [0xc0,0xd0,0x78,0xd5]
+# W_FEATS: mrrs x0, x1, TTBR0_EL2 // encoding: [0x00,0x20,0x7c,0xd5]
+# W_FEATS: mrrs x0, x1, TTBR1_EL2 // encoding: [0x20,0x20,0x7c,0xd5]
+# W_FEATS: mrrs x0, x1, VTTBR_EL2 // encoding: [0x00,0x21,0x7c,0xd5]
+# W_FEATS: mrrs x0, x1, VTTBR_EL2 // encoding: [0x00,0x21,0x7c,0xd5]
+# W_FEATS: mrrs x2, x3, VTTBR_EL2 // encoding: [0x02,0x21,0x7c,0xd5]
+# W_FEATS: mrrs x4, x5, VTTBR_EL2 // encoding: [0x04,0x21,0x7c,0xd5]
+# W_FEATS: mrrs x6, x7, VTTBR_EL2 // encoding: [0x06,0x21,0x7c,0xd5]
+# W_FEATS: mrrs x8, x9, VTTBR_EL2 // encoding: [0x08,0x21,0x7c,0xd5]
+# W_FEATS: mrrs x10, x11, VTTBR_EL2 // encoding: [0x0a,0x21,0x7c,0xd5]
+# W_FEATS: mrrs x12, x13, VTTBR_EL2 // encoding: [0x0c,0x21,0x7c,0xd5]
+# W_FEATS: mrrs x14, x15, VTTBR_EL2 // encoding: [0x0e,0x21,0x7c,0xd5]
+# W_FEATS: mrrs x16, x17, VTTBR_EL2 // encoding: [0x10,0x21,0x7c,0xd5]
+# W_FEATS: mrrs x18, x19, VTTBR_EL2 // encoding: [0x12,0x21,0x7c,0xd5]
+# W_FEATS: mrrs x20, x21, VTTBR_EL2 // encoding: [0x14,0x21,0x7c,0xd5]
+# W_FEATS: mrrs x22, x23, VTTBR_EL2 // encoding: [0x16,0x21,0x7c,0xd5]
+# W_FEATS: mrrs x24, x25, VTTBR_EL2 // encoding: [0x18,0x21,0x7c,0xd5]
+# W_FEATS: mrrs x26, x27, VTTBR_EL2 // encoding: [0x1a,0x21,0x7c,0xd5]
+
+# ERROR-NO-D128: warning: invalid instruction encoding
+
+
+0x00,0x20,0x58,0xd5
+0x20,0x20,0x58,0xd5
+0x00,0x74,0x58,0xd5
+0x60,0xd0,0x58,0xd5
+0xc0,0xd0,0x58,0xd5
+0x00,0x20,0x5c,0xd5
+0x20,0x20,0x5c,0xd5
+0x00,0x21,0x5c,0xd5
+0x00,0x21,0x5c,0xd5
+0x02,0x21,0x5c,0xd5
+0x04,0x21,0x5c,0xd5
+0x06,0x21,0x5c,0xd5
+0x08,0x21,0x5c,0xd5
+0x0a,0x21,0x5c,0xd5
+0x0c,0x21,0x5c,0xd5
+0x0e,0x21,0x5c,0xd5
+0x10,0x21,0x5c,0xd5
+0x12,0x21,0x5c,0xd5
+0x14,0x21,0x5c,0xd5
+0x16,0x21,0x5c,0xd5
+0x18,0x21,0x5c,0xd5
+0x1a,0x21,0x5c,0xd5
+
+# WITHOUT: msrr TTBR0_EL1, x0, x1 // encoding: [0x00,0x20,0x58,0xd5]
+# WITHOUT: msrr TTBR1_EL1, x0, x1 // encoding: [0x20,0x20,0x58,0xd5]
+# WITHOUT: msrr PAR_EL1, x0, x1 // encoding: [0x00,0x74,0x58,0xd5]
+# WITHOUT: msrr S3_0_C13_C0_3, x0, x1 // encoding: [0x60,0xd0,0x58,0xd5]
+# WITHOUT: msrr S3_0_C13_C0_6, x0, x1 // encoding: [0xc0,0xd0,0x58,0xd5]
+# WITHOUT: msrr S3_4_C2_C0_0, x0, x1 // encoding: [0x00,0x20,0x5c,0xd5]
+# WITHOUT: msrr S3_4_C2_C0_1, x0, x1 // encoding: [0x20,0x20,0x5c,0xd5]
+# WITHOUT: msrr S3_4_C2_C1_0, x0, x1 // encoding: [0x00,0x21,0x5c,0xd5]
+# WITHOUT: msrr S3_4_C2_C1_0, x0, x1 // encoding: [0x00,0x21,0x5c,0xd5]
+# WITHOUT: msrr S3_4_C2_C1_0, x2, x3 // encoding: [0x02,0x21,0x5c,0xd5]
+# WITHOUT: msrr S3_4_C2_C1_0, x4, x5 // encoding: [0x04,0x21,0x5c,0xd5]
+# WITHOUT: msrr S3_4_C2_C1_0, x6, x7 // encoding: [0x06,0x21,0x5c,0xd5]
+# WITHOUT: msrr S3_4_C2_C1_0, x8, x9 // encoding: [0x08,0x21,0x5c,0xd5]
+# WITHOUT: msrr S3_4_C2_C1_0, x10, x11 // encoding: [0x0a,0x21,0x5c,0xd5]
+# WITHOUT: msrr S3_4_C2_C1_0, x12, x13 // encoding: [0x0c,0x21,0x5c,0xd5]
+# WITHOUT: msrr S3_4_C2_C1_0, x14, x15 // encoding: [0x0e,0x21,0x5c,0xd5]
+# WITHOUT: msrr S3_4_C2_C1_0, x16, x17 // encoding: [0x10,0x21,0x5c,0xd5]
+# WITHOUT: msrr S3_4_C2_C1_0, x18, x19 // encoding: [0x12,0x21,0x5c,0xd5]
+# WITHOUT: msrr S3_4_C2_C1_0, x20, x21 // encoding: [0x14,0x21,0x5c,0xd5]
+# WITHOUT: msrr S3_4_C2_C1_0, x22, x23 // encoding: [0x16,0x21,0x5c,0xd5]
+# WITHOUT: msrr S3_4_C2_C1_0, x24, x25 // encoding: [0x18,0x21,0x5c,0xd5]
+# WITHOUT: msrr S3_4_C2_C1_0, x26, x27 // encoding: [0x1a,0x21,0x5c,0xd5]
+
+# W_FEATS: msrr TTBR0_EL1, x0, x1 // encoding: [0x00,0x20,0x58,0xd5]
+# W_FEATS: msrr TTBR1_EL1, x0, x1 // encoding: [0x20,0x20,0x58,0xd5]
+# W_FEATS: msrr PAR_EL1, x0, x1 // encoding: [0x00,0x74,0x58,0xd5]
+# W_FEATS: msrr RCWSMASK_EL1, x0, x1 // encoding: [0x60,0xd0,0x58,0xd5]
+# W_FEATS: msrr RCWMASK_EL1, x0, x1 // encoding: [0xc0,0xd0,0x58,0xd5]
+# W_FEATS: msrr TTBR0_EL2, x0, x1 // encoding: [0x00,0x20,0x5c,0xd5]
+# W_FEATS: msrr TTBR1_EL2, x0, x1 // encoding: [0x20,0x20,0x5c,0xd5]
+# W_FEATS: msrr VTTBR_EL2, x0, x1 // encoding: [0x00,0x21,0x5c,0xd5]
+# W_FEATS: msrr VTTBR_EL2, x0, x1 // encoding: [0x00,0x21,0x5c,0xd5]
+# W_FEATS: msrr VTTBR_EL2, x2, x3 // encoding: [0x02,0x21,0x5c,0xd5]
+# W_FEATS: msrr VTTBR_EL2, x4, x5 // encoding: [0x04,0x21,0x5c,0xd5]
+# W_FEATS: msrr VTTBR_EL2, x6, x7 // encoding: [0x06,0x21,0x5c,0xd5]
+# W_FEATS: msrr VTTBR_EL2, x8, x9 // encoding: [0x08,0x21,0x5c,0xd5]
+# W_FEATS: msrr VTTBR_EL2, x10, x11 // encoding: [0x0a,0x21,0x5c,0xd5]
+# W_FEATS: msrr VTTBR_EL2, x12, x13 // encoding: [0x0c,0x21,0x5c,0xd5]
+# W_FEATS: msrr VTTBR_EL2, x14, x15 // encoding: [0x0e,0x21,0x5c,0xd5]
+# W_FEATS: msrr VTTBR_EL2, x16, x17 // encoding: [0x10,0x21,0x5c,0xd5]
+# W_FEATS: msrr VTTBR_EL2, x18, x19 // encoding: [0x12,0x21,0x5c,0xd5]
+# W_FEATS: msrr VTTBR_EL2, x20, x21 // encoding: [0x14,0x21,0x5c,0xd5]
+# W_FEATS: msrr VTTBR_EL2, x22, x23 // encoding: [0x16,0x21,0x5c,0xd5]
+# W_FEATS: msrr VTTBR_EL2, x24, x25 // encoding: [0x18,0x21,0x5c,0xd5]
+# W_FEATS: msrr VTTBR_EL2, x26, x27 // encoding: [0x1a,0x21,0x5c,0xd5]
+
+# ERROR-NO-D128: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.4a-lse128.txt b/llvm/test/MC/Disassembler/AArch64/armv9.4a-lse128.txt
new file mode 100644
index 0000000000000..d4dffa0b3a9b6
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv9.4a-lse128.txt
@@ -0,0 +1,98 @@
+# RUN: llvm-mc -triple=aarch64 -mattr=+lse128 -disassemble %s | FileCheck %s
+# RUN: not llvm-mc -triple=aarch64 -disassemble %s 2>&1 | FileCheck --check-prefix=NO-LSE128 %s
+
+[0x61,0x11,0x22,0x19]
+# CHECK: ldclrp x1, x2, [x11]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0xf5,0x13,0x36,0x19]
+# CHECK: ldclrp x21, x22, [sp]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0x61,0x11,0xa2,0x19]
+# CHECK: ldclrpa x1, x2, [x11]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0xf5,0x13,0xb6,0x19]
+# CHECK: ldclrpa x21, x22, [sp]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0x61,0x11,0xe2,0x19]
+# CHECK: ldclrpal x1, x2, [x11]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0xf5,0x13,0xf6,0x19]
+# CHECK: ldclrpal x21, x22, [sp]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0x61,0x11,0x62,0x19]
+# CHECK: ldclrpl x1, x2, [x11]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0xf5,0x13,0x76,0x19]
+# CHECK: ldclrpl x21, x22, [sp]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0x61,0x31,0x22,0x19]
+# CHECK: ldsetp x1, x2, [x11]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0xf5,0x33,0x36,0x19]
+# CHECK: ldsetp x21, x22, [sp]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0x61,0x31,0xa2,0x19]
+# CHECK: ldsetpa x1, x2, [x11]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0xf5,0x33,0xb6,0x19]
+# CHECK: ldsetpa x21, x22, [sp]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0x61,0x31,0xe2,0x19]
+# CHECK: ldsetpal x1, x2, [x11]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0xf5,0x33,0xf6,0x19]
+# CHECK: ldsetpal x21, x22, [sp]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0x61,0x31,0x62,0x19]
+# CHECK: ldsetpl x1, x2, [x11]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0xf5,0x33,0x76,0x19]
+# CHECK: ldsetpl x21, x22, [sp]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0x61,0x81,0x22,0x19]
+# CHECK: swpp x1, x2, [x11]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0xf5,0x83,0x36,0x19]
+# CHECK: swpp x21, x22, [sp]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0x61,0x81,0xa2,0x19]
+# CHECK: swppa x1, x2, [x11]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0xf5,0x83,0xb6,0x19]
+# CHECK: swppa x21, x22, [sp]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0x61,0x81,0xe2,0x19]
+# CHECK: swppal x1, x2, [x11]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0xf5,0x83,0xf6,0x19]
+# CHECK: swppal x21, x22, [sp]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0x61,0x81,0x62,0x19]
+# CHECK: swppl x1, x2, [x11]
+# NO-LSE128: warning: invalid instruction encoding
+
+[0xf5,0x83,0x76,0x19]
+# CHECK: swppl x21, x22, [sp]
+# NO-LSE128: warning: invalid instruction encoding
diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
index 1cbc40f520517..71ebaf4e4e547 100644
--- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
+++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
@@ -3412,6 +3412,33 @@
# CHECK: msr {{pmevtyper28_el0|PMEVTYPER28_EL0}}, x12
# CHECK: msr {{pmevtyper29_el0|PMEVTYPER29_EL0}}, x12
# CHECK: msr {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12
+# CHECK: msr {{amair2_el1|AMAIR2_EL1}}, x12
+# CHECK: msr {{amair2_el12|AMAIR2_EL12}}, x12
+# CHECK: msr {{amair2_el2|AMAIR2_EL2}}, x12
+# CHECK: msr {{amair2_el3|AMAIR2_EL3}}, x12
+# CHECK: msr {{mair2_el1|MAIR2_EL1}}, x12
+# CHECK: msr {{mair2_el12|MAIR2_EL12}}, x12
+# CHECK: msr {{mair2_el2|MAIR2_EL2}}, x12
+# CHECK: msr {{mair2_el3|MAIR2_EL3}}, x12
+# CHECK: msr {{pire0_el1|PIRE0_EL1}}, x12
+# CHECK: msr {{pire0_el2|PIRE0_EL2}}, x12
+# CHECK: msr {{pir_el1|PIR_EL1}}, x12
+# CHECK: msr {{pir_el12|PIR_EL12}}, x12
+# CHECK: msr {{pir_el2|PIR_EL2}}, x12
+# CHECK: msr {{pir_el3|PIR_EL3}}, x12
+# CHECK: msr {{s2pir_el2|S2PIR_EL2}}, x12
+# CHECK: msr {{por_el0|POR_EL0}}, x12
+# CHECK: msr {{por_el1|POR_EL1}}, x12
+# CHECK: msr {{por_el12|POR_EL12}}, x12
+# CHECK: msr {{por_el2|POR_EL2}}, x12
+# CHECK: msr {{por_el3|POR_EL3}}, x12
+# CHECK: msr {{s2por_el1|S2POR_EL1}}, x12
+# CHECK: msr {{sctlr2_el1|SCTLR2_EL1}}, x12
+# CHECK: msr {{sctlr2_el12|SCTLR2_EL12}}, x12
+# CHECK: msr {{sctlr2_el2|SCTLR2_EL2}}, x12
+# CHECK: msr {{tcr2_el1|TCR2_EL1}}, x12
+# CHECK: msr {{tcr2_el12|TCR2_EL12}}, x12
+# CHECK: msr {{tcr2_el2|TCR2_EL2}}, x12
# CHECK: mrs x9, {{teecr32_el1|TEECR32_EL1}}
# CHECK: mrs x9, {{osdtrrx_el1|OSDTRRX_EL1}}
# CHECK: mrs x9, {{mdccsr_el0|MDCCSR_EL0}}
@@ -3717,6 +3744,33 @@
# CHECK: mrs x9, {{pmevtyper28_el0|PMEVTYPER28_EL0}}
# CHECK: mrs x9, {{pmevtyper29_el0|PMEVTYPER29_EL0}}
# CHECK: mrs x9, {{pmevtyper30_el0|PMEVTYPER30_EL0}}
+# CHECK: mrs x9, {{amair2_el1|AMAIR2_EL1}}
+# CHECK: mrs x9, {{amair2_el12|AMAIR2_EL12}}
+# CHECK: mrs x9, {{amair2_el2|AMAIR2_EL2}}
+# CHECK: mrs x9, {{amair2_el3|AMAIR2_EL3}}
+# CHECK: mrs x9, {{mair2_el1|MAIR2_EL1}}
+# CHECK: mrs x9, {{mair2_el12|MAIR2_EL12}}
+# CHECK: mrs x9, {{mair2_el2|MAIR2_EL2}}
+# CHECK: mrs x9, {{mair2_el3|MAIR2_EL3}}
+# CHECK: mrs x9, {{pire0_el1|PIRE0_EL1}}
+# CHECK: mrs x9, {{pire0_el2|PIRE0_EL2}}
+# CHECK: mrs x9, {{pir_el1|PIR_EL1}}
+# CHECK: mrs x9, {{pir_el12|PIR_EL12}}
+# CHECK: mrs x9, {{pir_el2|PIR_EL2}}
+# CHECK: mrs x9, {{pir_el3|PIR_EL3}}
+# CHECK: mrs x9, {{s2pir_el2|S2PIR_EL2}}
+# CHECK: mrs x9, {{por_el0|POR_EL0}}
+# CHECK: mrs x9, {{por_el1|POR_EL1}}
+# CHECK: mrs x9, {{por_el12|POR_EL12}}
+# CHECK: mrs x9, {{por_el2|POR_EL2}}
+# CHECK: mrs x9, {{por_el3|POR_EL3}}
+# CHECK: mrs x9, {{s2por_el1|S2POR_EL1}}
+# CHECK: mrs x9, {{sctlr2_el1|SCTLR2_EL1}}
+# CHECK: mrs x9, {{sctlr2_el12|SCTLR2_EL12}}
+# CHECK: mrs x9, {{sctlr2_el2|SCTLR2_EL2}}
+# CHECK: mrs x9, {{tcr2_el1|TCR2_EL1}}
+# CHECK: mrs x9, {{tcr2_el12|TCR2_EL12}}
+# CHECK: mrs x9, {{tcr2_el2|TCR2_EL2}}
0xc 0x0 0x12 0xd5
0x4c 0x0 0x10 0xd5
@@ -3972,6 +4026,33 @@
0x8c 0xef 0x1b 0xd5
0xac 0xef 0x1b 0xd5
0xcc 0xef 0x1b 0xd5
+0x2c 0xa3 0x18 0xd5
+0x2c 0xa3 0x1d 0xd5
+0x2c 0xa3 0x1c 0xd5
+0x2c 0xa3 0x1e 0xd5
+0x2c 0xa2 0x18 0xd5
+0x2c 0xa2 0x1d 0xd5
+0x2c 0xa1 0x1c 0xd5
+0x2c 0xa1 0x1e 0xd5
+0x4c 0xa2 0x18 0xd5
+0x4c 0xa2 0x1c 0xd5
+0x6c 0xa2 0x18 0xd5
+0x6c 0xa2 0x1d 0xd5
+0x6c 0xa2 0x1c 0xd5
+0x6c 0xa2 0x1e 0xd5
+0xac 0xa2 0x1c 0xd5
+0x8c 0xa2 0x1b 0xd5
+0x8c 0xa2 0x18 0xd5
+0x8c 0xa2 0x1d 0xd5
+0x8c 0xa2 0x1c 0xd5
+0x8c 0xa2 0x1e 0xd5
+0xac 0xa2 0x18 0xd5
+0x6c 0x10 0x18 0xd5
+0x6c 0x10 0x1d 0xd5
+0x6c 0x10 0x1c 0xd5
+0x6c 0x20 0x18 0xd5
+0x6c 0x20 0x1d 0xd5
+0x6c 0x20 0x1c 0xd5
0x9 0x0 0x32 0xd5
0x49 0x0 0x30 0xd5
0x9 0x1 0x33 0xd5
@@ -4278,6 +4359,33 @@
0x89 0xef 0x3b 0xd5
0xa9 0xef 0x3b 0xd5
0xc9 0xef 0x3b 0xd5
+0x29 0xa3 0x38 0xd5
+0x29 0xa3 0x3d 0xd5
+0x29 0xa3 0x3c 0xd5
+0x29 0xa3 0x3e 0xd5
+0x29 0xa2 0x38 0xd5
+0x29 0xa2 0x3d 0xd5
+0x29 0xa1 0x3c 0xd5
+0x29 0xa1 0x3e 0xd5
+0x49 0xa2 0x38 0xd5
+0x49 0xa2 0x3c 0xd5
+0x69 0xa2 0x38 0xd5
+0x69 0xa2 0x3d 0xd5
+0x69 0xa2 0x3c 0xd5
+0x69 0xa2 0x3e 0xd5
+0xa9 0xa2 0x3c 0xd5
+0x89 0xa2 0x3b 0xd5
+0x89 0xa2 0x38 0xd5
+0x89 0xa2 0x3d 0xd5
+0x89 0xa2 0x3c 0xd5
+0x89 0xa2 0x3e 0xd5
+0xa9 0xa2 0x38 0xd5
+0x69 0x10 0x38 0xd5
+0x69 0x10 0x3d 0xd5
+0x69 0x10 0x3c 0xd5
+0x69 0x20 0x38 0xd5
+0x69 0x20 0x3d 0xd5
+0x69 0x20 0x3c 0xd5
# CHECK: mrs x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}}
# CHECK: mrs x13, {{s3_2_c11_c15_7|S3_2_C11_C15_7}}
diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp
index a51a07b7b1294..42b0ed8376be1 100644
--- a/llvm/unittests/Support/TargetParserTest.cpp
+++ b/llvm/unittests/Support/TargetParserTest.cpp
@@ -1591,23 +1591,25 @@ TEST(TargetParserTest, testAArch64Extension) {
TEST(TargetParserTest, AArch64ExtensionFeatures) {
std::vector<uint64_t> Extensions = {
- AArch64::AEK_CRC, AArch64::AEK_LSE, AArch64::AEK_RDM,
- AArch64::AEK_CRYPTO, AArch64::AEK_SM4, AArch64::AEK_SHA3,
- AArch64::AEK_SHA2, AArch64::AEK_AES, AArch64::AEK_DOTPROD,
- AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_FP16,
- AArch64::AEK_FP16FML, AArch64::AEK_PROFILE, AArch64::AEK_RAS,
- AArch64::AEK_SVE, AArch64::AEK_SVE2, AArch64::AEK_SVE2AES,
- AArch64::AEK_SVE2SM4, AArch64::AEK_SVE2SHA3, AArch64::AEK_SVE2BITPERM,
- AArch64::AEK_RCPC, AArch64::AEK_RAND, AArch64::AEK_MTE,
- AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_PREDRES,
- AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_F32MM,
- AArch64::AEK_F64MM, AArch64::AEK_TME, AArch64::AEK_LS64,
- AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
+ AArch64::AEK_CRC, AArch64::AEK_LSE, AArch64::AEK_RDM,
+ AArch64::AEK_CRYPTO, AArch64::AEK_SM4, AArch64::AEK_SHA3,
+ AArch64::AEK_SHA2, AArch64::AEK_AES, AArch64::AEK_DOTPROD,
+ AArch64::AEK_FP, AArch64::AEK_SIMD, AArch64::AEK_FP16,
+ AArch64::AEK_FP16FML, AArch64::AEK_PROFILE, AArch64::AEK_RAS,
+ AArch64::AEK_SVE, AArch64::AEK_SVE2, AArch64::AEK_SVE2AES,
+ AArch64::AEK_SVE2SM4, AArch64::AEK_SVE2SHA3, AArch64::AEK_SVE2BITPERM,
+ AArch64::AEK_RCPC, AArch64::AEK_RAND, AArch64::AEK_MTE,
+ AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_PREDRES,
+ AArch64::AEK_BF16, AArch64::AEK_I8MM, AArch64::AEK_F32MM,
+ AArch64::AEK_F64MM, AArch64::AEK_TME, AArch64::AEK_LS64,
+ AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
AArch64::AEK_SME, AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
- AArch64::AEK_SME2, AArch64::AEK_HBC, AArch64::AEK_MOPS,
- AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1, AArch64::AEK_SME2p1,
+ AArch64::AEK_SME2, AArch64::AEK_HBC, AArch64::AEK_MOPS,
+ AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1, AArch64::AEK_SME2p1,
AArch64::AEK_B16B16, AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
- AArch64::AEK_RCPC3};
+ AArch64::AEK_RCPC3, AArch64::AEK_THE, AArch64::AEK_D128,
+ AArch64::AEK_LSE128,
+ };
std::vector<StringRef> Features;
@@ -1674,6 +1676,9 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+perfmon"));
EXPECT_TRUE(llvm::is_contained(Features, "+cssc"));
EXPECT_TRUE(llvm::is_contained(Features, "+rcpc3"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+the"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+d128"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+lse128"));
// Assuming we listed every extension above, this should produce the same
// result. (note that AEK_NONE doesn't have a name so it won't be in the
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