[PATCH] D138883: [SelectionDAG][PowerPC] Memset reuse vector element for tail store

[Ting Wang via Phabricator via llvm-commits]

tingwang added inline comments.


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Comment at: llvm/test/CodeGen/PowerPC/p10-fi-elim.ll:31
 ; CHECK-NEXT:    mr r6, r5
-; CHECK-NEXT:    li r0, 4
-; CHECK-NEXT:    li r11, 3
-; CHECK-NEXT:    std r0, 0(r3)
-; CHECK-NEXT:    stb r11, 0(0)
-; CHECK-NEXT:    li r12, -127
-; CHECK-NEXT:    stb r12, 0(r3)
-; CHECK-NEXT:    li r2, 1
-; CHECK-NEXT:    stb r11, 0(r3)
-; CHECK-NEXT:    stb r12, 0(r3)
-; CHECK-NEXT:    stw r2, 0(r3)
-; CHECK-NEXT:    mfvsrd r5, v2
-; CHECK-NEXT:    vaddudm v3, v2, v2
-; CHECK-NEXT:    pstxv v2, 64(r1), 0
-; CHECK-NEXT:    neg r5, r5
-; CHECK-NEXT:    mfvsrd r10, v3
-; CHECK-NEXT:    std r5, 0(r3)
+; CHECK-NEXT:    li r5, 3
+; CHECK-NEXT:    li r10, -127
----------------
Instruction sequence change in `PowerPC/p10-fi-elim.ll` is result of `CodeGenPrepare::optimizeExtractElementInst()` now can generate combined pattern since we enabled `canCombineStoreAndExtract()`. Seems we can avoid two mfvsrd instructions.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D138883/new/

https://reviews.llvm.org/D138883