[PATCH] D138817: [AAch64] Optimize muls with operands having enough sign bits.

[Biplob Mishra via Phabricator via llvm-commits]

bipmis marked 4 inline comments as done.
bipmis added a comment.

In D138817#3955002 <https://reviews.llvm.org/D138817#3955002>, @dmgreen wrote:

> Could this apply to umull too? We should also (not necessarily in this commit) look into improving GlobalISel too.  I think it should have enough info nowadays to perform the same ComputeNumSignBits check.

I think in this patch we are looking for handling the muls with sign-bits. We can possibly handle the umull scenario in a separate patch.



================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:1926
+def smullwithsignbits : PatFrag<(ops node:$l, node:$r), (mul node:$l, node:$r), [{
+  return CurDAG->ComputeNumSignBits(N->getOperand(0)) > 32 &&
+         CurDAG->ComputeNumSignBits(N->getOperand(1)) > 32;
----------------
dmgreen wrote:
> I think it maybe needs to be 33 bits. Sign bits are always off by one. Can you add some tests for the edge cases?
> I think it maybe needs to be 33 bits. Sign bits are always off by one. Can you add some tests for the edge cases?

I think it has to be 32 bits as we are comparing that number of sign bit in mul operand is greater than 32. The test smull_ldrsw_w(), fails with a value of 33 as it is an edge case with a i32 operand.


```
define i64 @smull_ldrsw_w(i32* %x0, i32 %x1) {
; CHECK-LABEL: smull_ldrsw_w:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ldrsw x8, [x0]
; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT:    sxtw x9, w1
; CHECK-NEXT:    mul x0, x8, x9
; CHECK-NEXT:    ret
entry:
  %ext64 = load i32, i32* %x0
  %sext = sext i32 %ext64 to i64
  %sext4 = sext i32 %x1 to i64
  %mul = mul i64 %sext, %sext4
  ret i64 %mul
}

```


Repository:
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https://reviews.llvm.org/D138817