[PATCH] D138883: [SelectionDAG][PowerPC] Memset reuse vector element for tail store
Nemanja Ivanovic via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 28 19:55:19 PST 2022
nemanjai added a comment.
I think this is useful, but we should ensure we can get rid of the swap that this introduces (in a separate patch).
================
Comment at: llvm/include/llvm/CodeGen/TargetLowering.h:672
+ /// construct constant value and store.
+ virtual bool isStoreElementFromVectorCheap(SelectionDAG &DAG, EVT VT,
+ uint64_t &Idx) const {
----------------
Do we need this? Can `canCombineStoreAndExtract()` suffice for this purpose?
================
Comment at: llvm/test/CodeGen/PowerPC/memset-tail.ll:42
+; P8-LE-NEXT: li 4, 16
+; P8-LE-NEXT: xxswapd 0, 34
+; P8-LE-NEXT: stxsdx 34, 3, 4
----------------
Why do we now get the redundant swap for the vector store that we didn't get before? Was it eliminated by the swap elimination before and now it is not because we have a use of the partial vector?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D138883/new/
https://reviews.llvm.org/D138883
More information about the llvm-commits
mailing list