[PATCH] D138876: [RISCV] Share code for fixed offsets adjustRegs (thus materializing fewer constants)

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
reames added reviewers: frasercrmck, asb, craig.topper, jrtc27, kito-cheng.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, niosHD, sabuasal, bollu, simoncook, johnrusso, rbar, hiraditya, arichardson, mcrosier.
Herald added a project: All.
reames requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.

This reuses the existing optimized implementation of adjustReg, and commons up code.  This has the effect of enabling two code changes for the new caller.  First, we enable the "split andi" lowering (with no alignment requirement), and second we use a sub with smaller constant in register instead of a add with negative constant in register.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138876

Files:
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/test/CodeGen/RISCV/branch-relaxation.ll
  llvm/test/CodeGen/RISCV/large-stack.ll
  llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
  llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
  llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
  llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
  llvm/test/CodeGen/RISCV/stack-realignment.ll
  llvm/test/CodeGen/RISCV/vararg.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D138876.478409.patch
Type: text/x-patch
Size: 46145 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221129/47aa721f/attachment.bin>