[llvm] f51170b - [X86] Fix SLM ldmxcsr/stmxcsr schedule classes
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 28 09:43:45 PST 2022
Author: Simon Pilgrim
Date: 2022-11-28T17:43:17Z
New Revision: f51170bffd507b872df228cb8c7512fe0389b7cf
URL: https://github.com/llvm/llvm-project/commit/f51170bffd507b872df228cb8c7512fe0389b7cf
DIFF: https://github.com/llvm/llvm-project/commit/f51170bffd507b872df228cb8c7512fe0389b7cf.diff
LOG: [X86] Fix SLM ldmxcsr/stmxcsr schedule classes
Fix a long standing FIXME comment using a mixture of llvm-exegesis and Agner numbers
Added:
Modified:
llvm/lib/Target/X86/X86ScheduleSLM.td
llvm/test/tools/llvm-mca/X86/SLM/resources-sse1.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ScheduleSLM.td b/llvm/lib/Target/X86/X86ScheduleSLM.td
index 902591471491b..e186168bf603b 100644
--- a/llvm/lib/Target/X86/X86ScheduleSLM.td
+++ b/llvm/lib/Target/X86/X86ScheduleSLM.td
@@ -91,9 +91,8 @@ def : WriteRes<WriteZero, []>;
defm : X86WriteResUnsupported<WriteVecMaskedGatherWriteback>;
// Load/store MXCSR.
-// FIXME: These are probably wrong. They are copy pasted from WriteStore/Load.
-def : WriteRes<WriteSTMXCSR, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
-def : WriteRes<WriteLDMXCSR, [SLM_MEC_RSV]> { let Latency = 3; }
+defm : X86WriteRes<WriteSTMXCSR, [SLM_MEC_RSV], 12,[11], 4>;
+defm : X86WriteRes<WriteLDMXCSR, [SLM_MEC_RSV], 10, [8], 5>;
// Treat misc copies as a move.
def : InstRW<[WriteMove], (instrs COPY)>;
diff --git a/llvm/test/tools/llvm-mca/X86/SLM/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/SLM/resources-sse1.s
index a84a32584cc9d..2362fe88ca699 100644
--- a/llvm/test/tools/llvm-mca/X86/SLM/resources-sse1.s
+++ b/llvm/test/tools/llvm-mca/X86/SLM/resources-sse1.s
@@ -230,7 +230,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: 7 42 39.00 * divps (%rax), %xmm2
# CHECK-NEXT: 1 19 17.00 divss %xmm0, %xmm2
# CHECK-NEXT: 1 22 17.00 * divss (%rax), %xmm2
-# CHECK-NEXT: 1 3 1.00 * * U ldmxcsr (%rax)
+# CHECK-NEXT: 5 10 8.00 * * U ldmxcsr (%rax)
# CHECK-NEXT: 1 1 1.00 * * U maskmovq %mm0, %mm1
# CHECK-NEXT: 1 3 1.00 maxps %xmm0, %xmm2
# CHECK-NEXT: 1 6 1.00 * maxps (%rax), %xmm2
@@ -305,7 +305,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: 6 44 40.00 * sqrtps (%rax), %xmm2
# CHECK-NEXT: 1 20 20.00 sqrtss %xmm0, %xmm2
# CHECK-NEXT: 1 23 20.00 * sqrtss (%rax), %xmm2
-# CHECK-NEXT: 1 1 1.00 * U stmxcsr (%rax)
+# CHECK-NEXT: 4 12 11.00 * U stmxcsr (%rax)
# CHECK-NEXT: 1 3 1.00 subps %xmm0, %xmm2
# CHECK-NEXT: 1 6 1.00 * subps (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 subss %xmm0, %xmm2
@@ -331,7 +331,7 @@ xorps (%rax), %xmm2
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: - 232.00 8.00 108.00 37.00 0.50 0.50 67.00
+# CHECK-NEXT: - 232.00 8.00 108.00 37.00 - - 84.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
@@ -371,7 +371,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: - 39.00 - 1.00 - - - 1.00 divps (%rax), %xmm2
# CHECK-NEXT: - 17.00 - 1.00 - - - - divss %xmm0, %xmm2
# CHECK-NEXT: - 17.00 - 1.00 - - - 1.00 divss (%rax), %xmm2
-# CHECK-NEXT: - - - - - - - 1.00 ldmxcsr (%rax)
+# CHECK-NEXT: - - - - - - - 8.00 ldmxcsr (%rax)
# CHECK-NEXT: - - - 1.00 - - - - maskmovq %mm0, %mm1
# CHECK-NEXT: - - - - 1.00 - - - maxps %xmm0, %xmm2
# CHECK-NEXT: - - - - 1.00 - - 1.00 maxps (%rax), %xmm2
@@ -446,7 +446,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: - 40.00 - 1.00 - - - 1.00 sqrtps (%rax), %xmm2
# CHECK-NEXT: - 20.00 - 1.00 - - - - sqrtss %xmm0, %xmm2
# CHECK-NEXT: - 20.00 - 1.00 - - - 1.00 sqrtss (%rax), %xmm2
-# CHECK-NEXT: - - - - - 0.50 0.50 1.00 stmxcsr (%rax)
+# CHECK-NEXT: - - - - - - - 11.00 stmxcsr (%rax)
# CHECK-NEXT: - - - - 1.00 - - - subps %xmm0, %xmm2
# CHECK-NEXT: - - - - 1.00 - - 1.00 subps (%rax), %xmm2
# CHECK-NEXT: - - - - 1.00 - - - subss %xmm0, %xmm2
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