[PATCH] D138811: [AArch64] SelectionDag codegen for gpr CTZ instruction

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:8499
+
+let Predicates = [HasCSSC] in {
+  def : Pat<(i32 (ctlz (bitreverse GPR32:$Rn))),
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lenary wrote:
> stuij wrote:
> > There's a question here if we should move these into dagcombiner and implement likewise for GlobalIsel, or if we should leave this here and have them be picked up by SelDag and GlobalIsel:
> We've talked already and my position is that these should be in dagcombiner/globalisel combines, but I'm interested in the views of e.g. @paquette @RKSimon. I realise combines like this might have to be behind hooks given that on some targets, cttz/ctlz of zero is undefined.
That's why we have support for cttz_zero_undef/G_CTTZ_ZERO_UNDEF etc - legalization should use the standard 'zero -> bw' case if the target supports it, but there's also the 'zero -> undef' opcode for targets that only support that.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D138811/new/

https://reviews.llvm.org/D138811