[PATCH] D138793: [AArch64][SVE2] Add patterns for eor3
Tiehu Zhang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 28 04:56:38 PST 2022
TiehuZhang created this revision.
TiehuZhang added reviewers: sdesmalen, dmgreen, mdchen, fhahn.
Herald added subscribers: hiraditya, kristof.beyls, tschuett.
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TiehuZhang requested review of this revision.
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Add patterns for:
eor x, (eor y, z) -> eor3 x, y, z
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D138793
Files:
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/sve2-eor3.ll
Index: llvm/test/CodeGen/AArch64/sve2-eor3.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve2-eor3.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sve2 < %s -o - | FileCheck %s --check-prefix=SVE2
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sve < %s -o - | FileCheck %s --check-prefix=SVE
+
+define <vscale x 16 x i8> @eor3(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2) {
+; SVE2-LABEL: eor3:
+; SVE2: // %bb.0:
+; SVE2-NEXT: eor3 z0.d, z0.d, z1.d, z2.d
+; SVE2-NEXT: ret
+;
+; SVE-LABEL: eor3:
+; SVE: // %bb.0:
+; SVE-NEXT: eor z0.d, z0.d, z1.d
+; SVE-NEXT: eor z0.d, z0.d, z2.d
+; SVE-NEXT: ret
+ %4 = xor <vscale x 16 x i8> %0, %1
+ %5 = xor <vscale x 16 x i8> %4, %2
+ ret <vscale x 16 x i8> %5
+}
Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -375,6 +375,9 @@
(sub node:$op1, (AArch64mul_p_oneuse node:$pred, node:$op2, node:$op3)),
// sub(a, select(mask, mul(b, c), splat(0))) -> mls(a, mask, b, c)
(sub node:$op1, (vselect node:$pred, (AArch64mul_p_oneuse (SVEAllActive), node:$op2, node:$op3), (SVEDup0)))]>;
+def AArch64eor3 : PatFrags<(ops node:$op1, node:$op2, node:$op3),
+ [(int_aarch64_sve_eor3 node:$op1, node:$op2, node:$op3),
+ (xor node:$op1, (xor node:$op2, node:$op3))]>;
class fma_patfrags<SDPatternOperator intrinsic, SDPatternOperator sdnode>
: PatFrags<(ops node:$pred, node:$op1, node:$op2, node:$op3),
@@ -3504,7 +3507,7 @@
defm FMLSLT_ZZZ_SHH : sve2_fp_mla_long<0b11, "fmlslt", int_aarch64_sve_fmlslt>;
// SVE2 bitwise ternary operations
- defm EOR3_ZZZZ : sve2_int_bitwise_ternary_op<0b000, "eor3", int_aarch64_sve_eor3>;
+ defm EOR3_ZZZZ : sve2_int_bitwise_ternary_op<0b000, "eor3", AArch64eor3>;
defm BCAX_ZZZZ : sve2_int_bitwise_ternary_op<0b010, "bcax", int_aarch64_sve_bcax>;
defm BSL_ZZZZ : sve2_int_bitwise_ternary_op<0b001, "bsl", int_aarch64_sve_bsl, AArch64bsp>;
defm BSL1N_ZZZZ : sve2_int_bitwise_ternary_op<0b011, "bsl1n", int_aarch64_sve_bsl1n>;
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