[PATCH] D138542: [InstSimplify] Use dominate condtion to simplify instructions

[chenglin.bi via Phabricator via llvm-commits]

bcl5980 added a comment.

Note:
This pattern will be triggered in
`SpecCPU2017\benchspec\CPU\502.gcc_r\src\tree-ssa-alias.c`
`SpecCPU2017\benchspec\CPU\510.parest_r\src\source\lac\block_sparse_matrix.cc`


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D138542/new/

https://reviews.llvm.org/D138542