[PATCH] D138639: [X86] Add In64BitMode for MOVSX64/MOVZX64 instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D138639#3950123 <https://reviews.llvm.org/D138639#3950123>, @HaohaiWen wrote:

>> Can we ignore those with isCodeGenOnly. I think they are just duplications of the non codegen only ones from the perspective of encoding.
>
> Of course we can ignore it in almost all cases because they'll never be generated to asm printer.
> However we should describe them correctly in schedule model. In fact, current schedtool D130897 <https://reviews.llvm.org/D130897> only emit scheduling info for not CodeGenOnly instruction. That means scheduling info for CodeGenOnly instructions like CVTSD2SI64rm may be not correct, although it should be same with CVTSD2SI64rm_Int.
> I'm working on fixing that, this requires correct mode predicates for CodeGenOnly and encodable instructions.

Is it not possible to use the encoding information in TSFlags rather than going through the assembly parser? Your patches for schedtool seem very coupled to the names of operand classes and other things. It looks like it will require updates often.


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