[PATCH] D138639: [X86] Add In64BitMode for MOVSX64/MOVZX64 instructions

[Haohai, Wen via Phabricator via llvm-commits]

HaohaiWen added a comment.

> Can we ignore those with isCodeGenOnly. I think they are just duplications of the non codegen only ones from the perspective of encoding.

Of course we can ignore it in almost all cases because they'll never be generated to asm printer.
However we should describe them correctly in schedule model. In fact, current schedtool D130897 <https://reviews.llvm.org/D130897> only emit scheduling info for not CodeGenOnly instruction. That means scheduling info for CodeGenOnly instructions like CVTSD2SI64rm may be not correct, although it should be same with CVTSD2SI64rm_Int.
I'm working on fixing that, this requires correct mode predicates for CodeGenOnly and encodable instructions.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138639/new/

https://reviews.llvm.org/D138639