[llvm] a5ee6e0 - [AArch64][SME]: Add precursory tests for D138292
Hassnaa Hamdi via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 23 08:13:47 PST 2022
Author: Hassnaa Hamdi
Date: 2022-11-23T15:49:16Z
New Revision: a5ee6e083616dc4cd3373f7ae10be753809bfee2
URL: https://github.com/llvm/llvm-project/commit/a5ee6e083616dc4cd3373f7ae10be753809bfee2
DIFF: https://github.com/llvm/llvm-project/commit/a5ee6e083616dc4cd3373f7ae10be753809bfee2.diff
LOG: [AArch64][SME]: Add precursory tests for D138292
Add testing files:
- int-minmax.ll
- fp-minmax.ll
Added:
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
new file mode 100644
index 000000000000..e2094a0dcfb7
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
@@ -0,0 +1,478 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+;
+; FMAXNM
+;
+
+define <4 x half> @fmaxnm_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
+; CHECK-LABEL: fmaxnm_v4f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnm v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %res = call <4 x half> @llvm.maxnum.v4f16(<4 x half> %op1, <4 x half> %op2)
+ ret <4 x half> %res
+}
+
+define <8 x half> @fmaxnm_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
+; CHECK-LABEL: fmaxnm_v8f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnm v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %res = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %op1, <8 x half> %op2)
+ ret <8 x half> %res
+}
+
+define void @fmaxnm_v16f16(<16 x half>* %a, <16 x half>* %b) #0 {
+; CHECK-LABEL: fmaxnm_v16f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: fmaxnm v0.8h, v0.8h, v2.8h
+; CHECK-NEXT: fmaxnm v1.8h, v1.8h, v3.8h
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <16 x half>, <16 x half>* %a
+ %op2 = load <16 x half>, <16 x half>* %b
+ %res = call <16 x half> @llvm.maxnum.v16f16(<16 x half> %op1, <16 x half> %op2)
+ store <16 x half> %res, <16 x half>* %a
+ ret void
+}
+
+define <2 x float> @fmaxnm_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
+; CHECK-LABEL: fmaxnm_v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %res = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %op1, <2 x float> %op2)
+ ret <2 x float> %res
+}
+
+define <4 x float> @fmaxnm_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
+; CHECK-LABEL: fmaxnm_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %res = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %op1, <4 x float> %op2)
+ ret <4 x float> %res
+}
+
+define void @fmaxnm_v8f32(<8 x float>* %a, <8 x float>* %b) #0 {
+; CHECK-LABEL: fmaxnm_v8f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: fmaxnm v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <8 x float>, <8 x float>* %a
+ %op2 = load <8 x float>, <8 x float>* %b
+ %res = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %op1, <8 x float> %op2)
+ store <8 x float> %res, <8 x float>* %a
+ ret void
+}
+
+define <1 x double> @fmaxnm_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
+; CHECK-LABEL: fmaxnm_v1f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
+; CHECK-NEXT: fmaxnm d0, d0, d1
+; CHECK-NEXT: ret
+ %res = call <1 x double> @llvm.maxnum.v1f64(<1 x double> %op1, <1 x double> %op2)
+ ret <1 x double> %res
+}
+
+define <2 x double> @fmaxnm_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
+; CHECK-LABEL: fmaxnm_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %res = call <2 x double> @llvm.maxnum.v2f64(<2 x double> %op1, <2 x double> %op2)
+ ret <2 x double> %res
+}
+
+define void @fmaxnm_v4f64(<4 x double>* %a, <4 x double>* %b) #0 {
+; CHECK-LABEL: fmaxnm_v4f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v2.2d
+; CHECK-NEXT: fmaxnm v1.2d, v1.2d, v3.2d
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <4 x double>, <4 x double>* %a
+ %op2 = load <4 x double>, <4 x double>* %b
+ %res = call <4 x double> @llvm.maxnum.v4f64(<4 x double> %op1, <4 x double> %op2)
+ store <4 x double> %res, <4 x double>* %a
+ ret void
+}
+
+;
+; FMINNM
+;
+
+define <4 x half> @fminnm_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
+; CHECK-LABEL: fminnm_v4f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminnm v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %res = call <4 x half> @llvm.minnum.v4f16(<4 x half> %op1, <4 x half> %op2)
+ ret <4 x half> %res
+}
+
+define <8 x half> @fminnm_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
+; CHECK-LABEL: fminnm_v8f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminnm v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %res = call <8 x half> @llvm.minnum.v8f16(<8 x half> %op1, <8 x half> %op2)
+ ret <8 x half> %res
+}
+
+define void @fminnm_v16f16(<16 x half>* %a, <16 x half>* %b) #0 {
+; CHECK-LABEL: fminnm_v16f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: fminnm v0.8h, v0.8h, v2.8h
+; CHECK-NEXT: fminnm v1.8h, v1.8h, v3.8h
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <16 x half>, <16 x half>* %a
+ %op2 = load <16 x half>, <16 x half>* %b
+ %res = call <16 x half> @llvm.minnum.v16f16(<16 x half> %op1, <16 x half> %op2)
+ store <16 x half> %res, <16 x half>* %a
+ ret void
+}
+
+define <2 x float> @fminnm_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
+; CHECK-LABEL: fminnm_v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %res = call <2 x float> @llvm.minnum.v2f32(<2 x float> %op1, <2 x float> %op2)
+ ret <2 x float> %res
+}
+
+define <4 x float> @fminnm_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
+; CHECK-LABEL: fminnm_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %res = call <4 x float> @llvm.minnum.v4f32(<4 x float> %op1, <4 x float> %op2)
+ ret <4 x float> %res
+}
+
+define void @fminnm_v8f32(<8 x float>* %a, <8 x float>* %b) #0 {
+; CHECK-LABEL: fminnm_v8f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: fminnm v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <8 x float>, <8 x float>* %a
+ %op2 = load <8 x float>, <8 x float>* %b
+ %res = call <8 x float> @llvm.minnum.v8f32(<8 x float> %op1, <8 x float> %op2)
+ store <8 x float> %res, <8 x float>* %a
+ ret void
+}
+
+define <1 x double> @fminnm_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
+; CHECK-LABEL: fminnm_v1f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
+; CHECK-NEXT: fminnm d0, d0, d1
+; CHECK-NEXT: ret
+ %res = call <1 x double> @llvm.minnum.v1f64(<1 x double> %op1, <1 x double> %op2)
+ ret <1 x double> %res
+}
+
+define <2 x double> @fminnm_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
+; CHECK-LABEL: fminnm_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %res = call <2 x double> @llvm.minnum.v2f64(<2 x double> %op1, <2 x double> %op2)
+ ret <2 x double> %res
+}
+
+define void @fminnm_v4f64(<4 x double>* %a, <4 x double>* %b) #0 {
+; CHECK-LABEL: fminnm_v4f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v2.2d
+; CHECK-NEXT: fminnm v1.2d, v1.2d, v3.2d
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <4 x double>, <4 x double>* %a
+ %op2 = load <4 x double>, <4 x double>* %b
+ %res = call <4 x double> @llvm.minnum.v4f64(<4 x double> %op1, <4 x double> %op2)
+ store <4 x double> %res, <4 x double>* %a
+ ret void
+}
+
+;
+; FMAX
+;
+
+define <4 x half> @fmax_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
+; CHECK-LABEL: fmax_v4f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmax v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %res = call <4 x half> @llvm.maximum.v4f16(<4 x half> %op1, <4 x half> %op2)
+ ret <4 x half> %res
+}
+
+define <8 x half> @fmax_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
+; CHECK-LABEL: fmax_v8f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmax v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %res = call <8 x half> @llvm.maximum.v8f16(<8 x half> %op1, <8 x half> %op2)
+ ret <8 x half> %res
+}
+
+define void @fmax_v16f16(<16 x half>* %a, <16 x half>* %b) #0 {
+; CHECK-LABEL: fmax_v16f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: fmax v0.8h, v0.8h, v2.8h
+; CHECK-NEXT: fmax v1.8h, v1.8h, v3.8h
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <16 x half>, <16 x half>* %a
+ %op2 = load <16 x half>, <16 x half>* %b
+ %res = call <16 x half> @llvm.maximum.v16f16(<16 x half> %op1, <16 x half> %op2)
+ store <16 x half> %res, <16 x half>* %a
+ ret void
+}
+
+define <2 x float> @fmax_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
+; CHECK-LABEL: fmax_v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmax v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %res = call <2 x float> @llvm.maximum.v2f32(<2 x float> %op1, <2 x float> %op2)
+ ret <2 x float> %res
+}
+
+define <4 x float> @fmax_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
+; CHECK-LABEL: fmax_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmax v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %res = call <4 x float> @llvm.maximum.v4f32(<4 x float> %op1, <4 x float> %op2)
+ ret <4 x float> %res
+}
+
+define void @fmax_v8f32(<8 x float>* %a, <8 x float>* %b) #0 {
+; CHECK-LABEL: fmax_v8f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: fmax v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: fmax v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <8 x float>, <8 x float>* %a
+ %op2 = load <8 x float>, <8 x float>* %b
+ %res = call <8 x float> @llvm.maximum.v8f32(<8 x float> %op1, <8 x float> %op2)
+ store <8 x float> %res, <8 x float>* %a
+ ret void
+}
+
+define <1 x double> @fmax_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
+; CHECK-LABEL: fmax_v1f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
+; CHECK-NEXT: fmax d0, d0, d1
+; CHECK-NEXT: ret
+ %res = call <1 x double> @llvm.maximum.v1f64(<1 x double> %op1, <1 x double> %op2)
+ ret <1 x double> %res
+}
+
+define <2 x double> @fmax_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
+; CHECK-LABEL: fmax_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmax v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %res = call <2 x double> @llvm.maximum.v2f64(<2 x double> %op1, <2 x double> %op2)
+ ret <2 x double> %res
+}
+
+define void @fmax_v4f64(<4 x double>* %a, <4 x double>* %b) #0 {
+; CHECK-LABEL: fmax_v4f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: fmax v0.2d, v0.2d, v2.2d
+; CHECK-NEXT: fmax v1.2d, v1.2d, v3.2d
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <4 x double>, <4 x double>* %a
+ %op2 = load <4 x double>, <4 x double>* %b
+ %res = call <4 x double> @llvm.maximum.v4f64(<4 x double> %op1, <4 x double> %op2)
+ store <4 x double> %res, <4 x double>* %a
+ ret void
+}
+
+;
+; FMIN
+;
+
+define <4 x half> @fmin_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
+; CHECK-LABEL: fmin_v4f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmin v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %res = call <4 x half> @llvm.minimum.v4f16(<4 x half> %op1, <4 x half> %op2)
+ ret <4 x half> %res
+}
+
+define <8 x half> @fmin_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
+; CHECK-LABEL: fmin_v8f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmin v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %res = call <8 x half> @llvm.minimum.v8f16(<8 x half> %op1, <8 x half> %op2)
+ ret <8 x half> %res
+}
+
+define void @fmin_v16f16(<16 x half>* %a, <16 x half>* %b) #0 {
+; CHECK-LABEL: fmin_v16f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: fmin v0.8h, v0.8h, v2.8h
+; CHECK-NEXT: fmin v1.8h, v1.8h, v3.8h
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <16 x half>, <16 x half>* %a
+ %op2 = load <16 x half>, <16 x half>* %b
+ %res = call <16 x half> @llvm.minimum.v16f16(<16 x half> %op1, <16 x half> %op2)
+ store <16 x half> %res, <16 x half>* %a
+ ret void
+}
+
+define <2 x float> @fmin_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
+; CHECK-LABEL: fmin_v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmin v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %res = call <2 x float> @llvm.minimum.v2f32(<2 x float> %op1, <2 x float> %op2)
+ ret <2 x float> %res
+}
+
+define <4 x float> @fmin_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
+; CHECK-LABEL: fmin_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmin v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %res = call <4 x float> @llvm.minimum.v4f32(<4 x float> %op1, <4 x float> %op2)
+ ret <4 x float> %res
+}
+
+define void @fmin_v8f32(<8 x float>* %a, <8 x float>* %b) #0 {
+; CHECK-LABEL: fmin_v8f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: fmin v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: fmin v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <8 x float>, <8 x float>* %a
+ %op2 = load <8 x float>, <8 x float>* %b
+ %res = call <8 x float> @llvm.minimum.v8f32(<8 x float> %op1, <8 x float> %op2)
+ store <8 x float> %res, <8 x float>* %a
+ ret void
+}
+
+define <1 x double> @fmin_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
+; CHECK-LABEL: fmin_v1f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
+; CHECK-NEXT: fmin d0, d0, d1
+; CHECK-NEXT: ret
+ %res = call <1 x double> @llvm.minimum.v1f64(<1 x double> %op1, <1 x double> %op2)
+ ret <1 x double> %res
+}
+
+define <2 x double> @fmin_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
+; CHECK-LABEL: fmin_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmin v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %res = call <2 x double> @llvm.minimum.v2f64(<2 x double> %op1, <2 x double> %op2)
+ ret <2 x double> %res
+}
+
+define void @fmin_v4f64(<4 x double>* %a, <4 x double>* %b) #0 {
+; CHECK-LABEL: fmin_v4f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: fmin v0.2d, v0.2d, v2.2d
+; CHECK-NEXT: fmin v1.2d, v1.2d, v3.2d
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <4 x double>, <4 x double>* %a
+ %op2 = load <4 x double>, <4 x double>* %b
+ %res = call <4 x double> @llvm.minimum.v4f64(<4 x double> %op1, <4 x double> %op2)
+ store <4 x double> %res, <4 x double>* %a
+ ret void
+}
+
+attributes #0 = { "target-features"="+sve" }
+
+declare <4 x half> @llvm.minnum.v4f16(<4 x half>, <4 x half>)
+declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>)
+declare <16 x half> @llvm.minnum.v16f16(<16 x half>, <16 x half>)
+declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>)
+declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>)
+declare <1 x double> @llvm.minnum.v1f64(<1 x double>, <1 x double>)
+declare <2 x double> @llvm.minnum.v2f64(<2 x double>, <2 x double>)
+declare <4 x double> @llvm.minnum.v4f64(<4 x double>, <4 x double>)
+
+declare <4 x half> @llvm.maxnum.v4f16(<4 x half>, <4 x half>)
+declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>)
+declare <16 x half> @llvm.maxnum.v16f16(<16 x half>, <16 x half>)
+declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>)
+declare <8 x float> @llvm.maxnum.v8f32(<8 x float>, <8 x float>)
+declare <1 x double> @llvm.maxnum.v1f64(<1 x double>, <1 x double>)
+declare <2 x double> @llvm.maxnum.v2f64(<2 x double>, <2 x double>)
+declare <4 x double> @llvm.maxnum.v4f64(<4 x double>, <4 x double>)
+
+declare <4 x half> @llvm.minimum.v4f16(<4 x half>, <4 x half>)
+declare <8 x half> @llvm.minimum.v8f16(<8 x half>, <8 x half>)
+declare <16 x half> @llvm.minimum.v16f16(<16 x half>, <16 x half>)
+declare <2 x float> @llvm.minimum.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.minimum.v4f32(<4 x float>, <4 x float>)
+declare <8 x float> @llvm.minimum.v8f32(<8 x float>, <8 x float>)
+declare <1 x double> @llvm.minimum.v1f64(<1 x double>, <1 x double>)
+declare <2 x double> @llvm.minimum.v2f64(<2 x double>, <2 x double>)
+declare <4 x double> @llvm.minimum.v4f64(<4 x double>, <4 x double>)
+
+declare <4 x half> @llvm.maximum.v4f16(<4 x half>, <4 x half>)
+declare <8 x half> @llvm.maximum.v8f16(<8 x half>, <8 x half>)
+declare <16 x half> @llvm.maximum.v16f16(<16 x half>, <16 x half>)
+declare <2 x float> @llvm.maximum.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.maximum.v4f32(<4 x float>, <4 x float>)
+declare <8 x float> @llvm.maximum.v8f32(<8 x float>, <8 x float>)
+declare <1 x double> @llvm.maximum.v1f64(<1 x double>, <1 x double>)
+declare <2 x double> @llvm.maximum.v2f64(<2 x double>, <2 x double>)
+declare <4 x double> @llvm.maximum.v4f64(<4 x double>, <4 x double>)
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
new file mode 100644
index 000000000000..691b812fe53b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
@@ -0,0 +1,662 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+;
+; SMAX
+;
+
+define <8 x i8> @smax_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+; CHECK-LABEL: smax_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smax v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %res = call <8 x i8> @llvm.smax.v8i8(<8 x i8> %op1, <8 x i8> %op2)
+ ret <8 x i8> %res
+}
+
+define <16 x i8> @smax_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+; CHECK-LABEL: smax_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smax v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %res = call <16 x i8> @llvm.smax.v16i8(<16 x i8> %op1, <16 x i8> %op2)
+ ret <16 x i8> %res
+}
+
+define void @smax_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
+; CHECK-LABEL: smax_v32i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: smax v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: smax v1.16b, v1.16b, v3.16b
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <32 x i8>, <32 x i8>* %a
+ %op2 = load <32 x i8>, <32 x i8>* %b
+ %res = call <32 x i8> @llvm.smax.v32i8(<32 x i8> %op1, <32 x i8> %op2)
+ store <32 x i8> %res, <32 x i8>* %a
+ ret void
+}
+
+define <4 x i16> @smax_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+; CHECK-LABEL: smax_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smax v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %res = call <4 x i16> @llvm.smax.v4i16(<4 x i16> %op1, <4 x i16> %op2)
+ ret <4 x i16> %res
+}
+
+define <8 x i16> @smax_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+; CHECK-LABEL: smax_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smax v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %res = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %op1, <8 x i16> %op2)
+ ret <8 x i16> %res
+}
+
+define void @smax_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
+; CHECK-LABEL: smax_v16i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: smax v0.8h, v0.8h, v2.8h
+; CHECK-NEXT: smax v1.8h, v1.8h, v3.8h
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <16 x i16>, <16 x i16>* %a
+ %op2 = load <16 x i16>, <16 x i16>* %b
+ %res = call <16 x i16> @llvm.smax.v16i16(<16 x i16> %op1, <16 x i16> %op2)
+ store <16 x i16> %res, <16 x i16>* %a
+ ret void
+}
+
+define <2 x i32> @smax_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+; CHECK-LABEL: smax_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %res = call <2 x i32> @llvm.smax.v2i32(<2 x i32> %op1, <2 x i32> %op2)
+ ret <2 x i32> %res
+}
+
+define <4 x i32> @smax_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+; CHECK-LABEL: smax_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %res = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %op1, <4 x i32> %op2)
+ ret <4 x i32> %res
+}
+
+define void @smax_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
+; CHECK-LABEL: smax_v8i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: smax v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: smax v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <8 x i32>, <8 x i32>* %a
+ %op2 = load <8 x i32>, <8 x i32>* %b
+ %res = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %op1, <8 x i32> %op2)
+ store <8 x i32> %res, <8 x i32>* %a
+ ret void
+}
+
+; Vector i64 max are not legal for NEON so use SVE when available.
+define <1 x i64> @smax_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+; CHECK-LABEL: smax_v1i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-NEXT: ptrue p0.d, vl1
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT: ret
+ %res = call <1 x i64> @llvm.smax.v1i64(<1 x i64> %op1, <1 x i64> %op2)
+ ret <1 x i64> %res
+}
+
+; Vector i64 max are not legal for NEON so use SVE when available.
+define <2 x i64> @smax_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+; CHECK-LABEL: smax_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: ret
+ %res = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %op1, <2 x i64> %op2)
+ ret <2 x i64> %res
+}
+
+define void @smax_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
+; CHECK-LABEL: smax_v4i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: smax z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: smax z1.d, p0/m, z1.d, z3.d
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <4 x i64>, <4 x i64>* %a
+ %op2 = load <4 x i64>, <4 x i64>* %b
+ %res = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %op1, <4 x i64> %op2)
+ store <4 x i64> %res, <4 x i64>* %a
+ ret void
+}
+
+;
+; SMIN
+;
+
+define <8 x i8> @smin_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+; CHECK-LABEL: smin_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smin v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %res = call <8 x i8> @llvm.smin.v8i8(<8 x i8> %op1, <8 x i8> %op2)
+ ret <8 x i8> %res
+}
+
+define <16 x i8> @smin_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+; CHECK-LABEL: smin_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smin v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %res = call <16 x i8> @llvm.smin.v16i8(<16 x i8> %op1, <16 x i8> %op2)
+ ret <16 x i8> %res
+}
+
+define void @smin_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
+; CHECK-LABEL: smin_v32i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: smin v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: smin v1.16b, v1.16b, v3.16b
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <32 x i8>, <32 x i8>* %a
+ %op2 = load <32 x i8>, <32 x i8>* %b
+ %res = call <32 x i8> @llvm.smin.v32i8(<32 x i8> %op1, <32 x i8> %op2)
+ store <32 x i8> %res, <32 x i8>* %a
+ ret void
+}
+
+define <4 x i16> @smin_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+; CHECK-LABEL: smin_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smin v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %res = call <4 x i16> @llvm.smin.v4i16(<4 x i16> %op1, <4 x i16> %op2)
+ ret <4 x i16> %res
+}
+
+define <8 x i16> @smin_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+; CHECK-LABEL: smin_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smin v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %res = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %op1, <8 x i16> %op2)
+ ret <8 x i16> %res
+}
+
+define void @smin_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
+; CHECK-LABEL: smin_v16i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: smin v0.8h, v0.8h, v2.8h
+; CHECK-NEXT: smin v1.8h, v1.8h, v3.8h
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <16 x i16>, <16 x i16>* %a
+ %op2 = load <16 x i16>, <16 x i16>* %b
+ %res = call <16 x i16> @llvm.smin.v16i16(<16 x i16> %op1, <16 x i16> %op2)
+ store <16 x i16> %res, <16 x i16>* %a
+ ret void
+}
+
+define <2 x i32> @smin_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+; CHECK-LABEL: smin_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %res = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %op1, <2 x i32> %op2)
+ ret <2 x i32> %res
+}
+
+define <4 x i32> @smin_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+; CHECK-LABEL: smin_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %res = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %op1, <4 x i32> %op2)
+ ret <4 x i32> %res
+}
+
+define void @smin_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
+; CHECK-LABEL: smin_v8i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: smin v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: smin v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <8 x i32>, <8 x i32>* %a
+ %op2 = load <8 x i32>, <8 x i32>* %b
+ %res = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %op1, <8 x i32> %op2)
+ store <8 x i32> %res, <8 x i32>* %a
+ ret void
+}
+
+; Vector i64 min are not legal for NEON so use SVE when available.
+define <1 x i64> @smin_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+; CHECK-LABEL: smin_v1i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-NEXT: ptrue p0.d, vl1
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT: ret
+ %res = call <1 x i64> @llvm.smin.v1i64(<1 x i64> %op1, <1 x i64> %op2)
+ ret <1 x i64> %res
+}
+
+; Vector i64 min are not legal for NEON so use SVE when available.
+define <2 x i64> @smin_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+; CHECK-LABEL: smin_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: ret
+ %res = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %op1, <2 x i64> %op2)
+ ret <2 x i64> %res
+}
+
+define void @smin_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
+; CHECK-LABEL: smin_v4i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: smin z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: smin z1.d, p0/m, z1.d, z3.d
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <4 x i64>, <4 x i64>* %a
+ %op2 = load <4 x i64>, <4 x i64>* %b
+ %res = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %op1, <4 x i64> %op2)
+ store <4 x i64> %res, <4 x i64>* %a
+ ret void
+}
+
+;
+; UMAX
+;
+
+define <8 x i8> @umax_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+; CHECK-LABEL: umax_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umax v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %res = call <8 x i8> @llvm.umax.v8i8(<8 x i8> %op1, <8 x i8> %op2)
+ ret <8 x i8> %res
+}
+
+define <16 x i8> @umax_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+; CHECK-LABEL: umax_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umax v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %res = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %op1, <16 x i8> %op2)
+ ret <16 x i8> %res
+}
+
+define void @umax_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
+; CHECK-LABEL: umax_v32i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: umax v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: umax v1.16b, v1.16b, v3.16b
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <32 x i8>, <32 x i8>* %a
+ %op2 = load <32 x i8>, <32 x i8>* %b
+ %res = call <32 x i8> @llvm.umax.v32i8(<32 x i8> %op1, <32 x i8> %op2)
+ store <32 x i8> %res, <32 x i8>* %a
+ ret void
+}
+
+define <4 x i16> @umax_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+; CHECK-LABEL: umax_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umax v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %res = call <4 x i16> @llvm.umax.v4i16(<4 x i16> %op1, <4 x i16> %op2)
+ ret <4 x i16> %res
+}
+
+define <8 x i16> @umax_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+; CHECK-LABEL: umax_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umax v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %res = call <8 x i16> @llvm.umax.v8i16(<8 x i16> %op1, <8 x i16> %op2)
+ ret <8 x i16> %res
+}
+
+define void @umax_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
+; CHECK-LABEL: umax_v16i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: umax v0.8h, v0.8h, v2.8h
+; CHECK-NEXT: umax v1.8h, v1.8h, v3.8h
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <16 x i16>, <16 x i16>* %a
+ %op2 = load <16 x i16>, <16 x i16>* %b
+ %res = call <16 x i16> @llvm.umax.v16i16(<16 x i16> %op1, <16 x i16> %op2)
+ store <16 x i16> %res, <16 x i16>* %a
+ ret void
+}
+
+define <2 x i32> @umax_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+; CHECK-LABEL: umax_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umax v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %res = call <2 x i32> @llvm.umax.v2i32(<2 x i32> %op1, <2 x i32> %op2)
+ ret <2 x i32> %res
+}
+
+define <4 x i32> @umax_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+; CHECK-LABEL: umax_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %res = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %op1, <4 x i32> %op2)
+ ret <4 x i32> %res
+}
+
+define void @umax_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
+; CHECK-LABEL: umax_v8i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: umax v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: umax v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <8 x i32>, <8 x i32>* %a
+ %op2 = load <8 x i32>, <8 x i32>* %b
+ %res = call <8 x i32> @llvm.umax.v8i32(<8 x i32> %op1, <8 x i32> %op2)
+ store <8 x i32> %res, <8 x i32>* %a
+ ret void
+}
+
+; Vector i64 max are not legal for NEON so use SVE when available.
+define <1 x i64> @umax_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+; CHECK-LABEL: umax_v1i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-NEXT: ptrue p0.d, vl1
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
+; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT: ret
+ %res = call <1 x i64> @llvm.umax.v1i64(<1 x i64> %op1, <1 x i64> %op2)
+ ret <1 x i64> %res
+}
+
+; Vector i64 max are not legal for NEON so use SVE when available.
+define <2 x i64> @umax_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+; CHECK-LABEL: umax_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: ret
+ %res = call <2 x i64> @llvm.umax.v2i64(<2 x i64> %op1, <2 x i64> %op2)
+ ret <2 x i64> %res
+}
+
+define void @umax_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
+; CHECK-LABEL: umax_v4i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: umax z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: umax z1.d, p0/m, z1.d, z3.d
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <4 x i64>, <4 x i64>* %a
+ %op2 = load <4 x i64>, <4 x i64>* %b
+ %res = call <4 x i64> @llvm.umax.v4i64(<4 x i64> %op1, <4 x i64> %op2)
+ store <4 x i64> %res, <4 x i64>* %a
+ ret void
+}
+
+;
+; UMIN
+;
+
+define <8 x i8> @umin_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
+; CHECK-LABEL: umin_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umin v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %res = call <8 x i8> @llvm.umin.v8i8(<8 x i8> %op1, <8 x i8> %op2)
+ ret <8 x i8> %res
+}
+
+define <16 x i8> @umin_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
+; CHECK-LABEL: umin_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umin v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %res = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %op1, <16 x i8> %op2)
+ ret <16 x i8> %res
+}
+
+define void @umin_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
+; CHECK-LABEL: umin_v32i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: umin v1.16b, v1.16b, v3.16b
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <32 x i8>, <32 x i8>* %a
+ %op2 = load <32 x i8>, <32 x i8>* %b
+ %res = call <32 x i8> @llvm.umin.v32i8(<32 x i8> %op1, <32 x i8> %op2)
+ store <32 x i8> %res, <32 x i8>* %a
+ ret void
+}
+
+define <4 x i16> @umin_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
+; CHECK-LABEL: umin_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umin v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: ret
+ %res = call <4 x i16> @llvm.umin.v4i16(<4 x i16> %op1, <4 x i16> %op2)
+ ret <4 x i16> %res
+}
+
+define <8 x i16> @umin_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
+; CHECK-LABEL: umin_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umin v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %res = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %op1, <8 x i16> %op2)
+ ret <8 x i16> %res
+}
+
+define void @umin_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
+; CHECK-LABEL: umin_v16i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: umin v0.8h, v0.8h, v2.8h
+; CHECK-NEXT: umin v1.8h, v1.8h, v3.8h
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <16 x i16>, <16 x i16>* %a
+ %op2 = load <16 x i16>, <16 x i16>* %b
+ %res = call <16 x i16> @llvm.umin.v16i16(<16 x i16> %op1, <16 x i16> %op2)
+ store <16 x i16> %res, <16 x i16>* %a
+ ret void
+}
+
+define <2 x i32> @umin_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
+; CHECK-LABEL: umin_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: ret
+ %res = call <2 x i32> @llvm.umin.v2i32(<2 x i32> %op1, <2 x i32> %op2)
+ ret <2 x i32> %res
+}
+
+define <4 x i32> @umin_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+; CHECK-LABEL: umin_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %res = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %op1, <4 x i32> %op2)
+ ret <4 x i32> %res
+}
+
+define void @umin_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
+; CHECK-LABEL: umin_v8i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: umin v0.4s, v0.4s, v2.4s
+; CHECK-NEXT: umin v1.4s, v1.4s, v3.4s
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <8 x i32>, <8 x i32>* %a
+ %op2 = load <8 x i32>, <8 x i32>* %b
+ %res = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %op1, <8 x i32> %op2)
+ store <8 x i32> %res, <8 x i32>* %a
+ ret void
+}
+
+; Vector i64 min are not legal for NEON so use SVE when available.
+define <1 x i64> @umin_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+; CHECK-LABEL: umin_v1i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-NEXT: ptrue p0.d, vl1
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT: ret
+ %res = call <1 x i64> @llvm.umin.v1i64(<1 x i64> %op1, <1 x i64> %op2)
+ ret <1 x i64> %res
+}
+
+; Vector i64 min are not legal for NEON so use SVE when available.
+define <2 x i64> @umin_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+; CHECK-LABEL: umin_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: ret
+ %res = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %op1, <2 x i64> %op2)
+ ret <2 x i64> %res
+}
+
+define void @umin_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
+; CHECK-LABEL: umin_v4i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: ldp q2, q3, [x1]
+; CHECK-NEXT: umin z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT: umin z1.d, p0/m, z1.d, z3.d
+; CHECK-NEXT: stp q0, q1, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <4 x i64>, <4 x i64>* %a
+ %op2 = load <4 x i64>, <4 x i64>* %b
+ %res = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %op1, <4 x i64> %op2)
+ store <4 x i64> %res, <4 x i64>* %a
+ ret void
+}
+
+attributes #0 = { "target-features"="+sve" }
+
+declare <8 x i8> @llvm.smin.v8i8(<8 x i8>, <8 x i8>)
+declare <16 x i8> @llvm.smin.v16i8(<16 x i8>, <16 x i8>)
+declare <32 x i8> @llvm.smin.v32i8(<32 x i8>, <32 x i8>)
+declare <4 x i16> @llvm.smin.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.smin.v8i16(<8 x i16>, <8 x i16>)
+declare <16 x i16> @llvm.smin.v16i16(<16 x i16>, <16 x i16>)
+declare <2 x i32> @llvm.smin.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>)
+declare <8 x i32> @llvm.smin.v8i32(<8 x i32>, <8 x i32>)
+declare <1 x i64> @llvm.smin.v1i64(<1 x i64>, <1 x i64>)
+declare <2 x i64> @llvm.smin.v2i64(<2 x i64>, <2 x i64>)
+declare <4 x i64> @llvm.smin.v4i64(<4 x i64>, <4 x i64>)
+
+declare <8 x i8> @llvm.smax.v8i8(<8 x i8>, <8 x i8>)
+declare <16 x i8> @llvm.smax.v16i8(<16 x i8>, <16 x i8>)
+declare <32 x i8> @llvm.smax.v32i8(<32 x i8>, <32 x i8>)
+declare <4 x i16> @llvm.smax.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.smax.v8i16(<8 x i16>, <8 x i16>)
+declare <16 x i16> @llvm.smax.v16i16(<16 x i16>, <16 x i16>)
+declare <2 x i32> @llvm.smax.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>)
+declare <8 x i32> @llvm.smax.v8i32(<8 x i32>, <8 x i32>)
+declare <1 x i64> @llvm.smax.v1i64(<1 x i64>, <1 x i64>)
+declare <2 x i64> @llvm.smax.v2i64(<2 x i64>, <2 x i64>)
+declare <4 x i64> @llvm.smax.v4i64(<4 x i64>, <4 x i64>)
+
+declare <8 x i8> @llvm.umin.v8i8(<8 x i8>, <8 x i8>)
+declare <16 x i8> @llvm.umin.v16i8(<16 x i8>, <16 x i8>)
+declare <32 x i8> @llvm.umin.v32i8(<32 x i8>, <32 x i8>)
+declare <4 x i16> @llvm.umin.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.umin.v8i16(<8 x i16>, <8 x i16>)
+declare <16 x i16> @llvm.umin.v16i16(<16 x i16>, <16 x i16>)
+declare <2 x i32> @llvm.umin.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)
+declare <8 x i32> @llvm.umin.v8i32(<8 x i32>, <8 x i32>)
+declare <1 x i64> @llvm.umin.v1i64(<1 x i64>, <1 x i64>)
+declare <2 x i64> @llvm.umin.v2i64(<2 x i64>, <2 x i64>)
+declare <4 x i64> @llvm.umin.v4i64(<4 x i64>, <4 x i64>)
+
+declare <8 x i8> @llvm.umax.v8i8(<8 x i8>, <8 x i8>)
+declare <16 x i8> @llvm.umax.v16i8(<16 x i8>, <16 x i8>)
+declare <32 x i8> @llvm.umax.v32i8(<32 x i8>, <32 x i8>)
+declare <4 x i16> @llvm.umax.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.umax.v8i16(<8 x i16>, <8 x i16>)
+declare <16 x i16> @llvm.umax.v16i16(<16 x i16>, <16 x i16>)
+declare <2 x i32> @llvm.umax.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>)
+declare <8 x i32> @llvm.umax.v8i32(<8 x i32>, <8 x i32>)
+declare <1 x i64> @llvm.umax.v1i64(<1 x i64>, <1 x i64>)
+declare <2 x i64> @llvm.umax.v2i64(<2 x i64>, <2 x i64>)
+declare <4 x i64> @llvm.umax.v4i64(<4 x i64>, <4 x i64>)
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