[PATCH] D138242: [RISCV] Use register allocation hints to improve use of compressed instructions.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 477067.
craig.topper added a comment.

Rename variable


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138242/new/

https://reviews.llvm.org/D138242

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/test/CodeGen/RISCV/add-before-shl.ll
  llvm/test/CodeGen/RISCV/addcarry.ll
  llvm/test/CodeGen/RISCV/aext-to-sext.ll
  llvm/test/CodeGen/RISCV/and.ll
  llvm/test/CodeGen/RISCV/atomic-rmw.ll
  llvm/test/CodeGen/RISCV/atomic-signext.ll
  llvm/test/CodeGen/RISCV/bittest.ll
  llvm/test/CodeGen/RISCV/branch-relaxation.ll
  llvm/test/CodeGen/RISCV/calling-conv-half.ll
  llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
  llvm/test/CodeGen/RISCV/double-convert.ll
  llvm/test/CodeGen/RISCV/float-arith.ll
  llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
  llvm/test/CodeGen/RISCV/float-convert.ll
  llvm/test/CodeGen/RISCV/fold-vector-cmp.ll
  llvm/test/CodeGen/RISCV/forced-atomics.ll
  llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/half-arith.ll
  llvm/test/CodeGen/RISCV/half-convert.ll
  llvm/test/CodeGen/RISCV/imm.ll
  llvm/test/CodeGen/RISCV/narrow-shl-cst.ll
  llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
  llvm/test/CodeGen/RISCV/rotl-rotr.ll
  llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
  llvm/test/CodeGen/RISCV/rv32zbkb.ll
  llvm/test/CodeGen/RISCV/rv32zbs.ll
  llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
  llvm/test/CodeGen/RISCV/rv64zbkb.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
  llvm/test/CodeGen/RISCV/rvv/vpstore.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
  llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
  llvm/test/CodeGen/RISCV/shifts.ll
  llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/unaligned-load-store.ll
  llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/vararg.ll
  llvm/test/CodeGen/RISCV/xaluo.ll

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