[PATCH] D138260: [RISCV] Prevent constant hoisting for (and (shl X, C), mask<<C)

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa391b49ce852: [RISCV] Prevent constant hoisting for (and (shl X, C), mask<<C) (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D138260?vs=476335&id=477047#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138260/new/

https://reviews.llvm.org/D138260

Files:
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll


Index: llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
===================================================================
--- llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
+++ llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll
@@ -81,3 +81,17 @@
   %2 = mul i64 %1, -4294967296
   ret i64 %2
 }
+
+define i32 @test10(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: @test10(
+; CHECK: shl i32 %a, 8
+; CHECK: and i32 %1, 65280
+; CHECK: shl i32 %b, 8
+; CHECK: and i32 %3, 65280
+  %1 = shl i32 %a, 8
+  %2 = and i32 %1, 65280
+  %3 = shl i32 %b, 8
+  %4 = and i32 %3, 65280
+  %5 = mul i32 %2, %4
+  ret i32 %5
+}
Index: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -46,6 +46,33 @@
                                     getST()->getFeatureBits());
 }
 
+// Look for patterns of shift followed by AND that can be turned into a pair of
+// shifts. We won't need to materialize an immediate for the AND so these can
+// be considered free.
+static bool canUseShiftPair(Instruction *Inst, const APInt &Imm) {
+  uint64_t Mask = Imm.getZExtValue();
+  auto *BO = dyn_cast<BinaryOperator>(Inst->getOperand(0));
+  if (!BO || !BO->hasOneUse())
+    return false;
+
+  if (BO->getOpcode() != Instruction::Shl)
+    return false;
+
+  if (!isa<ConstantInt>(BO->getOperand(1)))
+    return false;
+
+  unsigned ShAmt = cast<ConstantInt>(BO->getOperand(1))->getZExtValue();
+  // (and (shl x, c2), c1) will be matched to (srli (slli x, c2+c3), c3) if c1
+  // is a mask shifted by c2 bits with c3 leading zeros.
+  if (isShiftedMask_64(Mask)) {
+    unsigned Trailing = countTrailingZeros(Mask);
+    if (ShAmt == Trailing)
+      return true;
+  }
+
+  return false;
+}
+
 InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
                                                 const APInt &Imm, Type *Ty,
                                                 TTI::TargetCostKind CostKind,
@@ -75,6 +102,9 @@
     // zext.w
     if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZba())
       return TTI::TCC_Free;
+    if (Inst && Idx == 1 && Imm.getBitWidth() <= ST->getXLen() &&
+        canUseShiftPair(Inst, Imm))
+      return TTI::TCC_Free;
     [[fallthrough]];
   case Instruction::Add:
   case Instruction::Or:


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