[PATCH] D138242: [RISCV] Use register allocation hints to improve use of compressed instructions.

[Philip Reames via Phabricator via llvm-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM, basic premise make sense.

I'm wondering if we should go even further.  For out of order cores with renaming, defaulting to reuse the source register if legal seems like something we could always do.  I could see this being a problem for a core without renaming, do we have any such?



================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:416
+
+  for (auto &Use : MRI->reg_nodbg_instructions(VirtReg)) {
+    if (isCompressible(Use)) {
----------------
I believe Use is actually User here.  


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D138242/new/

https://reviews.llvm.org/D138242