[llvm] dd9a900 - [X86] Remove unnecessary XGETBV instruction overrides from znver1/znver2 models

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-11-20T14:05:05Z
New Revision: dd9a900a50f41dc5143103406b8eb00664ff96b4

URL: https://github.com/llvm/llvm-project/commit/dd9a900a50f41dc5143103406b8eb00664ff96b4
DIFF: https://github.com/llvm/llvm-project/commit/dd9a900a50f41dc5143103406b8eb00664ff96b4.diff

LOG: [X86] Remove unnecessary XGETBV instruction overrides from znver1/znver2 models

Reported by D138359 - znver models already treats all WriteSystem sched instructions as microcoded

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ScheduleZnver1.td
    llvm/lib/Target/X86/X86ScheduleZnver2.td

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td
index e7516371ab94..76e3ec429266 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver1.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td
@@ -758,9 +758,6 @@ def : InstRW<[WriteMicrocoded], (instrs PAUSE)>;
 // RDRAND.
 def : InstRW<[WriteMicrocoded], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;
 
-// XGETBV.
-def : InstRW<[WriteMicrocoded], (instrs XGETBV)>;
-
 // XADD.
 def ZnXADD : SchedWriteRes<[ZnALU]>;
 def : InstRW<[ZnXADD], (instregex "XADD(8|16|32|64)rr")>;

diff  --git a/llvm/lib/Target/X86/X86ScheduleZnver2.td b/llvm/lib/Target/X86/X86ScheduleZnver2.td
index c6a066075ecd..69246a06a5cc 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver2.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver2.td
@@ -768,9 +768,6 @@ def : InstRW<[WriteMicrocoded], (instrs PAUSE)>;
 // RDRAND.
 def : InstRW<[WriteMicrocoded], (instregex "RDRAND(16|32|64)r")>;
 
-// XGETBV.
-def : InstRW<[WriteMicrocoded], (instregex "XGETBV")>;
-
 // XADD.
 def Zn2XADD : SchedWriteRes<[Zn2ALU]>;
 def : InstRW<[Zn2XADD], (instregex "XADD(8|16|32|64)rr")>;