[PATCH] D137427: [RISCV][Codegen] Account for LMUL in Vector Mask instructions

Michael Maitland via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Nov 18 10:31:37 PST 2022


michaelmaitland added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:832
 
-// 16. Vector Mask Instructions
-def : ReadAdvance<ReadVMALUV, 0>;
-def : ReadAdvance<ReadVMPopV, 0>;
-def : ReadAdvance<ReadVMFFSV, 0>;
-def : ReadAdvance<ReadVMSFSV, 0>;
-def : ReadAdvance<ReadVMIotV, 0>;
+// 15. Vector Mask Instructions
+defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
----------------
kito-cheng wrote:
> I think that could be fixed in another small document fix only NFC patch?
Fixed in https://reviews.llvm.org/D138311


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137427/new/

https://reviews.llvm.org/D137427



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