[llvm] df24501 - [AArch64][SME]: Add precursory tests for D138222
Hassnaa Hamdi via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 18 04:20:23 PST 2022
Author: Hassnaa Hamdi
Date: 2022-11-18T12:20:16Z
New Revision: df24501f6a4ad4b5c9a60fb872b5793b556b523d
URL: https://github.com/llvm/llvm-project/commit/df24501f6a4ad4b5c9a60fb872b5793b556b523d
DIFF: https://github.com/llvm/llvm-project/commit/df24501f6a4ad4b5c9a60fb872b5793b556b523d.diff
LOG: [AArch64][SME]: Add precursory tests for D138222
Added:
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
new file mode 100644
index 000000000000..8b300e221561
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
@@ -0,0 +1,288 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+;
+; insertelement
+;
+
+; i8
+define <4 x i8> @insertelement_v4i8(<4 x i8> %op1) #0 {
+; CHECK-LABEL: insertelement_v4i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v0.h[3], w8
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
+ %r = insertelement <4 x i8> %op1, i8 5, i64 3
+ ret <4 x i8> %r
+}
+
+define <8 x i8> @insertelement_v8i8(<8 x i8> %op1) #0 {
+; CHECK-LABEL: insertelement_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v0.b[7], w8
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
+ %r = insertelement <8 x i8> %op1, i8 5, i64 7
+ ret <8 x i8> %r
+}
+
+define <16 x i8> @insertelement_v16i8(<16 x i8> %op1) #0 {
+; CHECK-LABEL: insertelement_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: mov v0.b[15], w8
+; CHECK-NEXT: ret
+ %r = insertelement <16 x i8> %op1, i8 5, i64 15
+ ret <16 x i8> %r
+}
+
+define <32 x i8> @insertelement_v32i8(<32 x i8> %op1) #0 {
+; CHECK-LABEL: insertelement_v32i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: mov v1.b[15], w8
+; CHECK-NEXT: ret
+ %r = insertelement <32 x i8> %op1, i8 5, i64 31
+ ret <32 x i8> %r
+}
+
+; i16
+define <2 x i16> @insertelement_v2i16(<2 x i16> %op1) #0 {
+; CHECK-LABEL: insertelement_v2i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v0.s[1], w8
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
+ %r = insertelement <2 x i16> %op1, i16 5, i64 1
+ ret <2 x i16> %r
+}
+
+define <4 x i16> @insertelement_v4i16(<4 x i16> %op1) #0 {
+; CHECK-LABEL: insertelement_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v0.h[3], w8
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
+ %r = insertelement <4 x i16> %op1, i16 5, i64 3
+ ret <4 x i16> %r
+}
+
+define <8 x i16> @insertelement_v8i16(<8 x i16> %op1) #0 {
+; CHECK-LABEL: insertelement_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: mov v0.h[7], w8
+; CHECK-NEXT: ret
+ %r = insertelement <8 x i16> %op1, i16 5, i64 7
+ ret <8 x i16> %r
+}
+
+define <16 x i16> @insertelement_v16i16(<16 x i16> %op1) #0 {
+; CHECK-LABEL: insertelement_v16i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: mov v1.h[7], w8
+; CHECK-NEXT: ret
+ %r = insertelement <16 x i16> %op1, i16 5, i64 15
+ ret <16 x i16> %r
+}
+
+;i32
+define <2 x i32> @insertelement_v2i32(<2 x i32> %op1) #0 {
+; CHECK-LABEL: insertelement_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v0.s[1], w8
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
+ %r = insertelement <2 x i32> %op1, i32 5, i64 1
+ ret <2 x i32> %r
+}
+
+define <4 x i32> @insertelement_v4i32(<4 x i32> %op1) #0 {
+; CHECK-LABEL: insertelement_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: ret
+ %r = insertelement <4 x i32> %op1, i32 5, i64 3
+ ret <4 x i32> %r
+}
+
+define <8 x i32> @insertelement_v8i32(<8 x i32>* %a) #0 {
+; CHECK-LABEL: insertelement_v8i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: mov v1.s[3], w8
+; CHECK-NEXT: ret
+ %op1 = load <8 x i32>, <8 x i32>* %a
+ %r = insertelement <8 x i32> %op1, i32 5, i64 7
+ ret <8 x i32> %r
+}
+
+;i64
+define <1 x i64> @insertelement_v1i64(<1 x i64> %op1) #0 {
+; CHECK-LABEL: insertelement_v1i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: ret
+ %r = insertelement <1 x i64> %op1, i64 5, i64 0
+ ret <1 x i64> %r
+}
+
+define <2 x i64> @insertelement_v2i64(<2 x i64> %op1) #0 {
+; CHECK-LABEL: insertelement_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: mov v0.d[1], x8
+; CHECK-NEXT: ret
+ %r = insertelement <2 x i64> %op1, i64 5, i64 1
+ ret <2 x i64> %r
+}
+
+define <4 x i64> @insertelement_v4i64(<4 x i64>* %a) #0 {
+; CHECK-LABEL: insertelement_v4i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: mov v1.d[1], x8
+; CHECK-NEXT: ret
+ %op1 = load <4 x i64>, <4 x i64>* %a
+ %r = insertelement <4 x i64> %op1, i64 5, i64 3
+ ret <4 x i64> %r
+}
+
+;f16
+define <2 x half> @insertelement_v2f16(<2 x half> %op1) #0 {
+; CHECK-LABEL: insertelement_v2f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: fmov h1, #5.00000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-NEXT: str h0, [sp, #8]
+; CHECK-NEXT: str h1, [sp, #10]
+; CHECK-NEXT: ldr d0, [sp, #8]
+; CHECK-NEXT: add sp, sp, #16
+; CHECK-NEXT: ret
+ %r = insertelement <2 x half> %op1, half 5.0, i64 1
+ ret <2 x half> %r
+}
+
+define <4 x half> @insertelement_v4f16(<4 x half> %op1) #0 {
+; CHECK-LABEL: insertelement_v4f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov h1, #5.00000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v0.h[3], v1.h[0]
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
+ %r = insertelement <4 x half> %op1, half 5.0, i64 3
+ ret <4 x half> %r
+}
+
+define <8 x half> @insertelement_v8f16(<8 x half> %op1) #0 {
+; CHECK-LABEL: insertelement_v8f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov h1, #5.00000000
+; CHECK-NEXT: mov v0.h[7], v1.h[0]
+; CHECK-NEXT: ret
+ %r = insertelement <8 x half> %op1, half 5.0, i64 7
+ ret <8 x half> %r
+}
+
+define <16 x half> @insertelement_v16f16(<16 x half>* %a) #0 {
+; CHECK-LABEL: insertelement_v16f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov h0, #5.00000000
+; CHECK-NEXT: ldr q1, [x0, #16]
+; CHECK-NEXT: mov v1.h[7], v0.h[0]
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <16 x half>, <16 x half>* %a
+ %r = insertelement <16 x half> %op1, half 5.0, i64 15
+ ret <16 x half> %r
+}
+
+;f32
+define <2 x float> @insertelement_v2f32(<2 x float> %op1) #0 {
+; CHECK-LABEL: insertelement_v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s1, #5.00000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
+ %r = insertelement <2 x float> %op1, float 5.0, i64 1
+ ret <2 x float> %r
+}
+
+define <4 x float> @insertelement_v4f32(<4 x float> %op1) #0 {
+; CHECK-LABEL: insertelement_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov s1, #5.00000000
+; CHECK-NEXT: mov v0.s[3], v1.s[0]
+; CHECK-NEXT: ret
+ %r = insertelement <4 x float> %op1, float 5.0, i64 3
+ ret <4 x float> %r
+}
+
+define <8 x float> @insertelement_v8f32(<8 x float>* %a) #0 {
+; CHECK-LABEL: insertelement_v8f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q0, q1, [x0]
+; CHECK-NEXT: fmov s2, #5.00000000
+; CHECK-NEXT: mov v1.s[3], v2.s[0]
+; CHECK-NEXT: ret
+ %op1 = load <8 x float>, <8 x float>* %a
+ %r = insertelement <8 x float> %op1, float 5.0, i64 7
+ ret <8 x float> %r
+}
+
+;f64
+define <1 x double> @insertelement_v1f64(<1 x double> %op1) #0 {
+; CHECK-LABEL: insertelement_v1f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov d0, #5.00000000
+; CHECK-NEXT: ret
+ %r = insertelement <1 x double> %op1, double 5.0, i64 0
+ ret <1 x double> %r
+}
+
+define <2 x double> @insertelement_v2f64(<2 x double> %op1) #0 {
+; CHECK-LABEL: insertelement_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov d1, #5.00000000
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
+ %r = insertelement <2 x double> %op1, double 5.0, i64 1
+ ret <2 x double> %r
+}
+
+define <4 x double> @insertelement_v4f64(<4 x double>* %a) #0 {
+; CHECK-LABEL: insertelement_v4f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov d0, #5.00000000
+; CHECK-NEXT: ldr q1, [x0, #16]
+; CHECK-NEXT: mov v1.d[1], v0.d[0]
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ret
+ %op1 = load <4 x double>, <4 x double>* %a
+ %r = insertelement <4 x double> %op1, double 5.0, i64 3
+ ret <4 x double> %r
+}
+
+attributes #0 = { "target-features"="+sve" }
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