[PATCH] D137574: PEI should be able to use backward walk in replaceFrameIndicesBackward.

[Alexander via Phabricator via llvm-commits]

alex-t updated this revision to Diff 475916.
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TargetRegisterInfo::eliminateFrameIndex signature changed to return "true" if the MachineInstr passed in by iterator was removed


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137574/new/

https://reviews.llvm.org/D137574

Files:
  llvm/include/llvm/CodeGen/TargetRegisterInfo.h
  llvm/lib/CodeGen/PrologEpilogInserter.cpp
  llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
  llvm/lib/Target/AArch64/AArch64RegisterInfo.h
  llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp
  llvm/lib/Target/AMDGPU/R600RegisterInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/lib/Target/ARC/ARCRegisterInfo.h
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
  llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
  llvm/lib/Target/ARM/ThumbRegisterInfo.h
  llvm/lib/Target/AVR/AVRRegisterInfo.cpp
  llvm/lib/Target/AVR/AVRRegisterInfo.h
  llvm/lib/Target/BPF/BPFRegisterInfo.cpp
  llvm/lib/Target/BPF/BPFRegisterInfo.h
  llvm/lib/Target/CSKY/CSKYRegisterInfo.cpp
  llvm/lib/Target/CSKY/CSKYRegisterInfo.h
  llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
  llvm/lib/Target/Hexagon/HexagonRegisterInfo.h
  llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp
  llvm/lib/Target/Lanai/LanaiRegisterInfo.h
  llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp
  llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h
  llvm/lib/Target/M68k/M68kRegisterInfo.cpp
  llvm/lib/Target/M68k/M68kRegisterInfo.h
  llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp
  llvm/lib/Target/MSP430/MSP430RegisterInfo.h
  llvm/lib/Target/Mips/MipsRegisterInfo.cpp
  llvm/lib/Target/Mips/MipsRegisterInfo.h
  llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
  llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/SPIRV/SPIRVRegisterInfo.h
  llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
  llvm/lib/Target/Sparc/SparcRegisterInfo.h
  llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
  llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
  llvm/lib/Target/VE/VERegisterInfo.cpp
  llvm/lib/Target/VE/VERegisterInfo.h
  llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h
  llvm/lib/Target/X86/X86RegisterInfo.cpp
  llvm/lib/Target/X86/X86RegisterInfo.h
  llvm/lib/Target/XCore/XCoreRegisterInfo.cpp
  llvm/lib/Target/XCore/XCoreRegisterInfo.h
  llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
  llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
  llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
  llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
  llvm/test/CodeGen/AMDGPU/flat-scratch.ll
  llvm/test/CodeGen/AMDGPU/frame-index.mir
  llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
  llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
  llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
  llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
  llvm/test/CodeGen/AMDGPU/scratch-simple.ll
  llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
  llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
  llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
  llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
  llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
  llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
  llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
  llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
  llvm/unittests/CodeGen/MFCommon.inc