[llvm] 7160987 - [AArch64][MachineCombiner] Use MIMetadata to copy pcsections metadata to reassociated instructions.
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 16 05:22:53 PST 2022
Author: David Green
Date: 2022-11-16T13:22:48Z
New Revision: 71609871dd733715bfcd48e1f43117191d008cb4
URL: https://github.com/llvm/llvm-project/commit/71609871dd733715bfcd48e1f43117191d008cb4
DIFF: https://github.com/llvm/llvm-project/commit/71609871dd733715bfcd48e1f43117191d008cb4.diff
LOG: [AArch64][MachineCombiner] Use MIMetadata to copy pcsections metadata to reassociated instructions.
D134260/D138107 exposed that the MachineCombiner was not copying
pcsections metadata where it should. This patch switches the MIBuild
methods to use MIMetadata that can copy the debug loc and pcsections at
the same time.
Differential Revision: https://reviews.llvm.org/D138112
Added:
Modified:
llvm/lib/CodeGen/TargetInstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index c14b64c18b21..f46a9446c878 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -870,12 +870,12 @@ void TargetInstrInfo::reassociateOps(
// Create new instructions for insertion.
MachineInstrBuilder MIB1 =
- BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
+ BuildMI(*MF, MIMetadata(Prev), TII->get(Opcode), NewVR)
.addReg(RegX, getKillRegState(KillX))
.addReg(RegY, getKillRegState(KillY))
.setMIFlags(Prev.getFlags());
MachineInstrBuilder MIB2 =
- BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)
+ BuildMI(*MF, MIMetadata(Root), TII->get(Opcode), RegC)
.addReg(RegA, getKillRegState(KillA))
.addReg(NewVR, getKillRegState(true))
.setMIFlags(Root.getFlags());
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 78c196c4e964..31eb2a92b57f 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -5557,18 +5557,18 @@ genFusedMultiply(MachineFunction &MF, MachineRegisterInfo &MRI,
MachineInstrBuilder MIB;
if (kind == FMAInstKind::Default)
- MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
+ MIB = BuildMI(MF, MIMetadata(Root), TII->get(MaddOpc), ResultReg)
.addReg(SrcReg0, getKillRegState(Src0IsKill))
.addReg(SrcReg1, getKillRegState(Src1IsKill))
.addReg(SrcReg2, getKillRegState(Src2IsKill));
else if (kind == FMAInstKind::Indexed)
- MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
+ MIB = BuildMI(MF, MIMetadata(Root), TII->get(MaddOpc), ResultReg)
.addReg(SrcReg2, getKillRegState(Src2IsKill))
.addReg(SrcReg0, getKillRegState(Src0IsKill))
.addReg(SrcReg1, getKillRegState(Src1IsKill))
.addImm(MUL->getOperand(3).getImm());
else if (kind == FMAInstKind::Accumulator)
- MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
+ MIB = BuildMI(MF, MIMetadata(Root), TII->get(MaddOpc), ResultReg)
.addReg(SrcReg2, getKillRegState(Src2IsKill))
.addReg(SrcReg0, getKillRegState(Src0IsKill))
.addReg(SrcReg1, getKillRegState(Src1IsKill));
@@ -5609,7 +5609,7 @@ genIndexedMultiply(MachineInstr &Root,
Register ResultReg = Root.getOperand(0).getReg();
MachineInstrBuilder MIB;
- MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MulOpc), ResultReg)
+ MIB = BuildMI(MF, MIMetadata(Root), TII->get(MulOpc), ResultReg)
.add(MulOp)
.addReg(DupSrcReg)
.addImm(DupSrcLane);
@@ -5639,7 +5639,7 @@ static Register genNeg(MachineFunction &MF, MachineRegisterInfo &MRI,
unsigned MnegOpc, const TargetRegisterClass *RC) {
Register NewVR = MRI.createVirtualRegister(RC);
MachineInstrBuilder MIB =
- BuildMI(MF, Root.getDebugLoc(), TII->get(MnegOpc), NewVR)
+ BuildMI(MF, MIMetadata(Root), TII->get(MnegOpc), NewVR)
.add(Root.getOperand(2));
InsInstrs.push_back(MIB);
@@ -5735,7 +5735,7 @@ static MachineInstr *genMaddR(MachineFunction &MF, MachineRegisterInfo &MRI,
MRI.constrainRegClass(VR, RC);
MachineInstrBuilder MIB =
- BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
+ BuildMI(MF, MIMetadata(Root), TII->get(MaddOpc), ResultReg)
.addReg(SrcReg0, getKillRegState(Src0IsKill))
.addReg(SrcReg1, getKillRegState(Src1IsKill))
.addReg(VR);
@@ -5777,11 +5777,11 @@ genSubAdd2SubSub(MachineFunction &MF, MachineRegisterInfo &MRI,
"Unexpected instruction opcode.");
MachineInstrBuilder MIB1 =
- BuildMI(MF, Root.getDebugLoc(), TII->get(Opcode), NewVR)
+ BuildMI(MF, MIMetadata(Root), TII->get(Opcode), NewVR)
.addReg(RegA, getKillRegState(RegAIsKill))
.addReg(RegB, getKillRegState(RegBIsKill));
MachineInstrBuilder MIB2 =
- BuildMI(MF, Root.getDebugLoc(), TII->get(Opcode), ResultReg)
+ BuildMI(MF, MIMetadata(Root), TII->get(Opcode), ResultReg)
.addReg(NewVR, getKillRegState(true))
.addReg(RegC, getKillRegState(RegCIsKill));
@@ -5896,7 +5896,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
MachineInstrBuilder MIB1;
// MOV is an alias for one of three instructions: movz, movn, and orr.
if (MovI->Opcode == OrrOpc)
- MIB1 = BuildMI(MF, Root.getDebugLoc(), TII->get(OrrOpc), NewVR)
+ MIB1 = BuildMI(MF, MIMetadata(Root), TII->get(OrrOpc), NewVR)
.addReg(ZeroReg)
.addImm(MovI->Op2);
else {
@@ -5908,7 +5908,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
assert((MovI->Opcode == AArch64::MOVNXi ||
MovI->Opcode == AArch64::MOVZXi) &&
"Expected opcode");
- MIB1 = BuildMI(MF, Root.getDebugLoc(), TII->get(MovI->Opcode), NewVR)
+ MIB1 = BuildMI(MF, MIMetadata(Root), TII->get(MovI->Opcode), NewVR)
.addImm(MovI->Op1)
.addImm(MovI->Op2);
}
@@ -5942,7 +5942,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
Register NewVR = MRI.createVirtualRegister(SubRC);
// SUB NewVR, 0, C
MachineInstrBuilder MIB1 =
- BuildMI(MF, Root.getDebugLoc(), TII->get(SubOpc), NewVR)
+ BuildMI(MF, MIMetadata(Root), TII->get(SubOpc), NewVR)
.addReg(ZeroReg)
.add(Root.getOperand(2));
InsInstrs.push_back(MIB1);
@@ -6005,7 +6005,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
MachineInstrBuilder MIB1;
// MOV is an alias for one of three instructions: movz, movn, and orr.
if (MovI->Opcode == OrrOpc)
- MIB1 = BuildMI(MF, Root.getDebugLoc(), TII->get(OrrOpc), NewVR)
+ MIB1 = BuildMI(MF, MIMetadata(Root), TII->get(OrrOpc), NewVR)
.addReg(ZeroReg)
.addImm(MovI->Op2);
else {
@@ -6017,7 +6017,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
assert((MovI->Opcode == AArch64::MOVNXi ||
MovI->Opcode == AArch64::MOVZXi) &&
"Expected opcode");
- MIB1 = BuildMI(MF, Root.getDebugLoc(), TII->get(MovI->Opcode), NewVR)
+ MIB1 = BuildMI(MF, MIMetadata(Root), TII->get(MovI->Opcode), NewVR)
.addImm(MovI->Op1)
.addImm(MovI->Op2);
}
@@ -6509,7 +6509,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
RC = &AArch64::FPR64RegClass;
Register NewVR = MRI.createVirtualRegister(RC);
MachineInstrBuilder MIB1 =
- BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv4f16), NewVR)
+ BuildMI(MF, MIMetadata(Root), TII->get(AArch64::FNEGv4f16), NewVR)
.add(Root.getOperand(2));
InsInstrs.push_back(MIB1);
InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
@@ -6556,7 +6556,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
RC = &AArch64::FPR128RegClass;
Register NewVR = MRI.createVirtualRegister(RC);
MachineInstrBuilder MIB1 =
- BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv8f16), NewVR)
+ BuildMI(MF, MIMetadata(Root), TII->get(AArch64::FNEGv8f16), NewVR)
.add(Root.getOperand(2));
InsInstrs.push_back(MIB1);
InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
@@ -6616,7 +6616,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
RC = &AArch64::FPR64RegClass;
Register NewVR = MRI.createVirtualRegister(RC);
MachineInstrBuilder MIB1 =
- BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv2f32), NewVR)
+ BuildMI(MF, MIMetadata(Root), TII->get(AArch64::FNEGv2f32), NewVR)
.add(Root.getOperand(2));
InsInstrs.push_back(MIB1);
InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
@@ -6636,7 +6636,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
RC = &AArch64::FPR128RegClass;
Register NewVR = MRI.createVirtualRegister(RC);
MachineInstrBuilder MIB1 =
- BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv4f32), NewVR)
+ BuildMI(MF, MIMetadata(Root), TII->get(AArch64::FNEGv4f32), NewVR)
.add(Root.getOperand(2));
InsInstrs.push_back(MIB1);
InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
@@ -6656,7 +6656,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
RC = &AArch64::FPR128RegClass;
Register NewVR = MRI.createVirtualRegister(RC);
MachineInstrBuilder MIB1 =
- BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv2f64), NewVR)
+ BuildMI(MF, MIMetadata(Root), TII->get(AArch64::FNEGv2f64), NewVR)
.add(Root.getOperand(2));
InsInstrs.push_back(MIB1);
InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
index 9aad111a5001..9cf6af2e6edd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -global-isel -global-isel-abort=1 -stop-after=aarch64-expand-pseudo -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-NOLSE
-; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -global-isel -global-isel-abort=1 -stop-after=aarch64-expand-pseudo -mattr=+rcpc,+ldapr -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LDAPR
+; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -global-isel -global-isel-abort=1 -stop-after=aarch64-expand-pseudo -mattr=+rcpc -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-LDAPR
define i32 @val_compare_and_swap(i32* %p, i32 %cmp, i32 %new) {
; CHECK-LABEL: name: val_compare_and_swap
@@ -389,8 +389,8 @@ define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) {
; CHECK-NEXT: renamable $w10 = LDRBBroW renamable $x0, killed renamable $w1, 1, 0, pcsections !0 :: (load unordered (s8) from %ir.ptr_regoff)
; CHECK-NEXT: renamable $w11 = LDURBBi killed renamable $x0, -256, pcsections !0 :: (load monotonic (s8) from %ir.ptr_unscaled)
; CHECK-NEXT: renamable $w8 = LDRBBui killed renamable $x8, 0, pcsections !0 :: (load unordered (s8) from %ir.ptr_random)
- ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0
- ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w10, killed renamable $w9, 0
+ ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0, pcsections !0
+ ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w10, killed renamable $w9, 0, pcsections !0
; CHECK-NEXT: $w0 = ADDWrs killed renamable $w9, killed renamable $w8, 0, pcsections !0
; CHECK-NEXT: RET undef $lr, implicit $w0
%ptr_unsigned = getelementptr i8, i8* %p, i32 4095
@@ -421,8 +421,8 @@ define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) {
; CHECK-NEXT: renamable $w10 = LDRHHroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s16) from %ir.ptr_regoff)
; CHECK-NEXT: renamable $w11 = LDURHHi killed renamable $x0, -256, pcsections !0 :: (load monotonic (s16) from %ir.ptr_unscaled)
; CHECK-NEXT: renamable $w8 = LDRHHui killed renamable $x8, 0, pcsections !0 :: (load unordered (s16) from %ir.ptr_random)
- ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0
- ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w10, killed renamable $w9, 0
+ ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0, pcsections !0
+ ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w10, killed renamable $w9, 0, pcsections !0
; CHECK-NEXT: $w0 = ADDWrs killed renamable $w9, killed renamable $w8, 0, pcsections !0
; CHECK-NEXT: RET undef $lr, implicit $w0
%ptr_unsigned = getelementptr i16, i16* %p, i32 4095
@@ -453,8 +453,8 @@ define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) {
; CHECK-NEXT: renamable $w10 = LDRWroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s32) from %ir.ptr_regoff)
; CHECK-NEXT: renamable $w11 = LDURWi killed renamable $x0, -256, pcsections !0 :: (load monotonic (s32) from %ir.ptr_unscaled)
; CHECK-NEXT: renamable $w8 = LDRWui killed renamable $x8, 0, pcsections !0 :: (load unordered (s32) from %ir.ptr_random)
- ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0
- ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w10, killed renamable $w9, 0
+ ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0, pcsections !0
+ ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w10, killed renamable $w9, 0, pcsections !0
; CHECK-NEXT: $w0 = ADDWrs killed renamable $w9, killed renamable $w8, 0, pcsections !0
; CHECK-NEXT: RET undef $lr, implicit $w0
%ptr_unsigned = getelementptr i32, i32* %p, i32 4095
@@ -485,8 +485,8 @@ define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) {
; CHECK-NEXT: renamable $x10 = LDRXroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s64) from %ir.ptr_regoff)
; CHECK-NEXT: renamable $x11 = LDURXi killed renamable $x0, -256, pcsections !0 :: (load monotonic (s64) from %ir.ptr_unscaled)
; CHECK-NEXT: renamable $x8 = LDRXui killed renamable $x8, 0, pcsections !0 :: (load unordered (s64) from %ir.ptr_random)
- ; CHECK-NEXT: $x9 = ADDXrs killed renamable $x9, killed renamable $x11, 0
- ; CHECK-NEXT: $x9 = ADDXrs killed renamable $x10, killed renamable $x9, 0
+ ; CHECK-NEXT: $x9 = ADDXrs killed renamable $x9, killed renamable $x11, 0, pcsections !0
+ ; CHECK-NEXT: $x9 = ADDXrs killed renamable $x10, killed renamable $x9, 0, pcsections !0
; CHECK-NEXT: $x0 = ADDXrs killed renamable $x9, killed renamable $x8, 0, pcsections !0
; CHECK-NEXT: RET undef $lr, implicit $x0
%ptr_unsigned = getelementptr i64, i64* %p, i32 4095
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