[PATCH] D137949: [RISCV] Branchless lowering for select (x < 0), TrueConstant, FalseConstant)

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9639
+      // register.
+      if (isInt<12>((uint64_t)TrueSImm) && isInt<12>((uint64_t)FalseSImm) &&
+          isInt<12>((uint64_t)FalseSImm - (uint64_t)TrueSImm)) {
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reames wrote:
> You shouldn't need these casts.  
Is it open to all constants? There will be some code size increase


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D137949/new/

https://reviews.llvm.org/D137949