[PATCH] D137949: [RISCV] Branchless lowering for select (x < 0), TrueConstant, FalseConstant)

[Philip Reames via Phabricator via llvm-commits]

reames requested changes to this revision.
reames added inline comments.
This revision now requires changes to proceed.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9630
 
+    // select (x < 0), y, z) -> (~x >> (XLEN - 1)) & (z - y) + y
+    APInt RMask = APInt::getBitsSetFrom(RHS.getValueSizeInBits(), 1);
----------------
It looks like we can avoid the not here by swapping the operands.  

```
select (x < 0), y, z -> (x >> (XLEN - 1) & (y - z) + z
```


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9633
+    if (!Subtarget.hasShortForwardBranchOpt() &&
+        CCVal == ISD::CondCode::SETLT && DAG.MaskedValueIsZero(RHS, RMask) &&
+        isa<ConstantSDNode>(TrueV) && isa<ConstantSDNode>(FalseV)) {
----------------
The code appears out of sync with the comment, not sure which is correct.

The MaskedValueIsZero check here allows rhs to be 0 or 1.  


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9639
+      // register.
+      if (isInt<12>((uint64_t)TrueSImm) && isInt<12>((uint64_t)FalseSImm) &&
+          isInt<12>((uint64_t)FalseSImm - (uint64_t)TrueSImm)) {
----------------
You shouldn't need these casts.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137949/new/

https://reviews.llvm.org/D137949