[llvm] 637ed52 - [RISCV] Remove old test case. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-11-14T09:36:44-08:00
New Revision: 637ed52d9d74e7ce4f272383852c9f133be3008d

URL: https://github.com/llvm/llvm-project/commit/637ed52d9d74e7ce4f272383852c9f133be3008d
DIFF: https://github.com/llvm/llvm-project/commit/637ed52d9d74e7ce4f272383852c9f133be3008d.diff

LOG: [RISCV] Remove old test case. NFC

This seemed to be testing a pattern for an RV64 Zbp instruction, but
on RV32. On RV32, it's just swizzling registers so isn't very
interesting.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rv32zbkb.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rv32zbkb.ll b/llvm/test/CodeGen/RISCV/rv32zbkb.ll
index fc9b82268c65..2f30d8783ff9 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbkb.ll
@@ -105,23 +105,6 @@ define i64 @pack_i64_3(ptr %0, ptr %1) {
   ret i64 %8
 }
 
-; As we are not matching directly i64 code patterns on RV32 some i64 patterns
-; don't have yet any matching bit manipulation instructions on RV32.
-; This test is presented here in case future expansions of the Bitmanip
-; extensions introduce instructions suitable for this pattern.
-
-define i64 @packu_i64(i64 %a, i64 %b) nounwind {
-; CHECK-LABEL: packu_i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    mv a0, a1
-; CHECK-NEXT:    mv a1, a3
-; CHECK-NEXT:    ret
-  %shr = lshr i64 %a, 32
-  %shr1 = and i64 %b, -4294967296
-  %or = or i64 %shr1, %shr
-  ret i64 %or
-}
-
 define i32 @packh_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: packh_i32:
 ; RV32I:       # %bb.0: