[llvm] 13e32a8 - [RISCV] Improve use of PACK instruction on rv64.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-11-14T09:36:33-08:00
New Revision: 13e32a8a3c95b23af51f081865db1bd259d269a4

URL: https://github.com/llvm/llvm-project/commit/13e32a8a3c95b23af51f081865db1bd259d269a4
DIFF: https://github.com/llvm/llvm-project/commit/13e32a8a3c95b23af51f081865db1bd259d269a4.diff

LOG: [RISCV] Improve use of PACK instruction on rv64.

Handle the case where the lower bits come from a zero extending
load or other operation with known zero bits.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    llvm/test/CodeGen/RISCV/rv32zbkb.ll
    llvm/test/CodeGen/RISCV/rv64zbkb.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index f196fac2028d..bb38c6f87f2d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -648,7 +648,7 @@ def : Pat<(i32 (or (zexti16 GPR:$rs1), (shl GPR:$rs2, (i32 16)))),
           (PACK GPR:$rs1, GPR:$rs2)>;
 
 let Predicates = [HasStdExtZbkb, IsRV64] in {
-def : Pat<(i64 (or (and GPR:$rs1, 0x00000000FFFFFFFF), (shl GPR:$rs2, (i64 32)))),
+def : Pat<(i64 (or (zexti32 GPR:$rs1), (shl GPR:$rs2, (i64 32)))),
           (PACK GPR:$rs1, GPR:$rs2)>;
 
 def : Pat<(binop_allwusers<or> (shl GPR:$rs2, (i64 16)),

diff  --git a/llvm/test/CodeGen/RISCV/rv32zbkb.ll b/llvm/test/CodeGen/RISCV/rv32zbkb.ll
index 1dda18bdfe7a..fc9b82268c65 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbkb.ll
@@ -89,6 +89,22 @@ define i64 @pack_i64_2(i32 %a, i32 %b) nounwind {
   ret i64 %or
 }
 
+define i64 @pack_i64_3(ptr %0, ptr %1) {
+; CHECK-LABEL: pack_i64_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lw a2, 0(a0)
+; CHECK-NEXT:    lw a0, 0(a1)
+; CHECK-NEXT:    mv a1, a2
+; CHECK-NEXT:    ret
+  %3 = load i32, ptr %0, align 4
+  %4 = zext i32 %3 to i64
+  %5 = shl i64 %4, 32
+  %6 = load i32, ptr %1, align 4
+  %7 = zext i32 %6 to i64
+  %8 = or i64 %5, %7
+  ret i64 %8
+}
+
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet any matching bit manipulation instructions on RV32.
 ; This test is presented here in case future expansions of the Bitmanip

diff  --git a/llvm/test/CodeGen/RISCV/rv64zbkb.ll b/llvm/test/CodeGen/RISCV/rv64zbkb.ll
index 35ea51f6f0f4..7ea059cb5aa8 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbkb.ll
@@ -102,6 +102,30 @@ define i64 @pack_i64_2(i32 signext %a, i32 signext %b) nounwind {
   ret i64 %or
 }
 
+define i64 @pack_i64_3(ptr %0, ptr %1) {
+; RV64I-LABEL: pack_i64_3:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lw a0, 0(a0)
+; RV64I-NEXT:    lwu a1, 0(a1)
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64ZBKB-LABEL: pack_i64_3:
+; RV64ZBKB:       # %bb.0:
+; RV64ZBKB-NEXT:    lw a0, 0(a0)
+; RV64ZBKB-NEXT:    lwu a1, 0(a1)
+; RV64ZBKB-NEXT:    pack a0, a1, a0
+; RV64ZBKB-NEXT:    ret
+  %3 = load i32, ptr %0, align 4
+  %4 = zext i32 %3 to i64
+  %5 = shl i64 %4, 32
+  %6 = load i32, ptr %1, align 4
+  %7 = zext i32 %6 to i64
+  %8 = or i64 %5, %7
+  ret i64 %8
+}
+
 define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: packh_i32:
 ; RV64I:       # %bb.0: