[llvm] 3ac93d1 - [RISCV] Add another PACKH pattern.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-11-13T23:57:52-08:00
New Revision: 3ac93d1f2fdad2d9e0fead48911f97c990fb5a69

URL: https://github.com/llvm/llvm-project/commit/3ac93d1f2fdad2d9e0fead48911f97c990fb5a69
DIFF: https://github.com/llvm/llvm-project/commit/3ac93d1f2fdad2d9e0fead48911f97c990fb5a69.diff

LOG: [RISCV] Add another PACKH pattern.

This handles the case where the upper bits are zeroed with an AND
after the OR.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    llvm/test/CodeGen/RISCV/rv32zbkb.ll
    llvm/test/CodeGen/RISCV/rv64zbkb.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 29282199ea2c..f196fac2028d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -638,6 +638,9 @@ def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFFFF),
 def : Pat<(or (shl (zexti8 GPR:$rs2), (XLenVT 8)),
               (zexti8 GPR:$rs1)),
           (PACKH GPR:$rs1, GPR:$rs2)>;
+def : Pat<(and (or (shl GPR:$rs2, (XLenVT 8)),
+                   (zexti8 GPR:$rs1)), 0xFFFF),
+          (PACKH GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbkb]
 
 let Predicates = [HasStdExtZbkb, IsRV32] in

diff  --git a/llvm/test/CodeGen/RISCV/rv32zbkb.ll b/llvm/test/CodeGen/RISCV/rv32zbkb.ll
index 7ae4c7bab361..1dda18bdfe7a 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbkb.ll
@@ -208,3 +208,27 @@ define zeroext i16 @packh_i16(i8 zeroext %a, i8 zeroext %b) nounwind {
   %or = or i16 %shl, %zext
   ret i16 %or
 }
+
+
+define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
+; RV32I-LABEL: packh_i16_2:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    add a0, a1, a0
+; RV32I-NEXT:    slli a0, a0, 8
+; RV32I-NEXT:    or a0, a0, a2
+; RV32I-NEXT:    slli a0, a0, 16
+; RV32I-NEXT:    srli a0, a0, 16
+; RV32I-NEXT:    ret
+;
+; RV32ZBKB-LABEL: packh_i16_2:
+; RV32ZBKB:       # %bb.0:
+; RV32ZBKB-NEXT:    add a0, a1, a0
+; RV32ZBKB-NEXT:    packh a0, a2, a0
+; RV32ZBKB-NEXT:    ret
+  %4 = add i8 %1, %0
+  %5 = zext i8 %4 to i16
+  %6 = shl i16 %5, 8
+  %7 = zext i8 %2 to i16
+  %8 = or i16 %6, %7
+  ret i16 %8
+}

diff  --git a/llvm/test/CodeGen/RISCV/rv64zbkb.ll b/llvm/test/CodeGen/RISCV/rv64zbkb.ll
index 757cd7871fa6..40de91ba7d2e 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbkb.ll
@@ -199,3 +199,26 @@ define zeroext i16 @packh_i16(i8 zeroext %a, i8 zeroext %b) nounwind {
   %or = or i16 %shl, %zext
   ret i16 %or
 }
+
+define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
+; RV64I-LABEL: packh_i16_2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    add a0, a1, a0
+; RV64I-NEXT:    slli a0, a0, 8
+; RV64I-NEXT:    or a0, a0, a2
+; RV64I-NEXT:    slli a0, a0, 48
+; RV64I-NEXT:    srli a0, a0, 48
+; RV64I-NEXT:    ret
+;
+; RV64ZBKB-LABEL: packh_i16_2:
+; RV64ZBKB:       # %bb.0:
+; RV64ZBKB-NEXT:    add a0, a1, a0
+; RV64ZBKB-NEXT:    packh a0, a2, a0
+; RV64ZBKB-NEXT:    ret
+  %4 = add i8 %1, %0
+  %5 = zext i8 %4 to i16
+  %6 = shl i16 %5, 8
+  %7 = zext i8 %2 to i16
+  %8 = or i16 %6, %7
+  ret i16 %8
+}