[llvm] 1f25888 - [RISCV] Add PACKW and PACKH to isSignExtendingOpW in RISCVSExtWRemoval.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-11-13T20:00:34-08:00
New Revision: 1f25888712cb757854c45e3070178968cdd50371

URL: https://github.com/llvm/llvm-project/commit/1f25888712cb757854c45e3070178968cdd50371
DIFF: https://github.com/llvm/llvm-project/commit/1f25888712cb757854c45e3070178968cdd50371.diff

LOG: [RISCV] Add PACKW and PACKH to isSignExtendingOpW in RISCVSExtWRemoval.

PACKW sign extends like other W instructions.
PACKH zeroes bits 63:16 which means bits 63:31 are all zero.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
index 8a6c728e1734..ebd64945b651 100644
--- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -250,6 +250,7 @@ static bool isSignExtendingOpW(MachineInstr &MI, MachineRegisterInfo &MRI,
   case RISCV::CLZW:
   case RISCV::CTZW:
   case RISCV::CPOPW:
+  case RISCV::PACKW:
   case RISCV::FCVT_W_H:
   case RISCV::FCVT_WU_H:
   case RISCV::FCVT_W_S:
@@ -276,6 +277,7 @@ static bool isSignExtendingOpW(MachineInstr &MI, MachineRegisterInfo &MRI,
   case RISCV::CLZ:
   case RISCV::CPOP:
   case RISCV::CTZ:
+  case RISCV::PACKH:
     return true;
   // shifting right sufficiently makes the value 32-bit sign-extended
   case RISCV::SRAI: