[llvm] 1a8ba9e - [RISCV] Improve selection of PACKW.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-11-13T18:37:37-08:00
New Revision: 1a8ba9e19f49dc0fc82615db13ad15f301077145

URL: https://github.com/llvm/llvm-project/commit/1a8ba9e19f49dc0fc82615db13ad15f301077145
DIFF: https://github.com/llvm/llvm-project/commit/1a8ba9e19f49dc0fc82615db13ad15f301077145.diff

LOG: [RISCV] Improve selection of PACKW.

Use hasAllWUsers to check if the upper bits are ignored so we can
use PACKW even when no sign_extend_inreg is present before the OR.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    llvm/test/CodeGen/RISCV/rv32zbkb.ll
    llvm/test/CodeGen/RISCV/rv64zbkb.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 87f5f7c62df0..6e3a2a38b81e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2528,6 +2528,7 @@ bool RISCVDAGToDAGISel::doPeepholeSExtW(SDNode *N) {
   case RISCV::SUBW:
   case RISCV::MULW:
   case RISCV::SLLIW:
+  case RISCV::PACKW:
     // Result is already sign extended just remove the sext.w.
     // NOTE: We only handle the nodes that are selected with hasAllWUsers.
     ReplaceUses(N, N0.getNode());

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 25d5a3a3067e..44ef57610409 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -648,9 +648,8 @@ let Predicates = [HasStdExtZbkb, IsRV64] in {
 def : Pat<(i64 (or (and GPR:$rs1, 0x00000000FFFFFFFF), (shl GPR:$rs2, (i64 32)))),
           (PACK GPR:$rs1, GPR:$rs2)>;
 
-def : Pat<(i64 (sext_inreg (or (shl GPR:$rs2, (i64 16)),
+def : Pat<(binop_allwusers<or> (shl GPR:$rs2, (i64 16)),
                                (zexti16 GPR:$rs1)),
-                           i32)),
           (PACKW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(i64 (or (sext_inreg (shl GPR:$rs2, (i64 16)), i32),
                    (zexti16 GPR:$rs1))),

diff  --git a/llvm/test/CodeGen/RISCV/rv32zbkb.ll b/llvm/test/CodeGen/RISCV/rv32zbkb.ll
index 56eac8873afb..5a4892519cea 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbkb.ll
@@ -41,6 +41,27 @@ define i32 @pack_i32_2(i16 zeroext %a, i16 zeroext %b) nounwind {
   ret i32 %or
 }
 
+define i32 @pack_i32_3(i16 zeroext %0, i16 zeroext %1, i32 %2) {
+; RV32I-LABEL: pack_i32_3:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a0, a0, 16
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    add a0, a0, a2
+; RV32I-NEXT:    ret
+;
+; RV32ZBKB-LABEL: pack_i32_3:
+; RV32ZBKB:       # %bb.0:
+; RV32ZBKB-NEXT:    pack a0, a1, a0
+; RV32ZBKB-NEXT:    add a0, a0, a2
+; RV32ZBKB-NEXT:    ret
+  %4 = zext i16 %0 to i32
+  %5 = shl nuw i32 %4, 16
+  %6 = zext i16 %1 to i32
+  %7 = or i32 %5, %6
+  %8 = add i32 %7, %2
+  ret i32 %8
+}
+
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet any matching bit manipulation instructions on RV32.
 ; This test is presented here in case future expansions of the Bitmanip

diff  --git a/llvm/test/CodeGen/RISCV/rv64zbkb.ll b/llvm/test/CodeGen/RISCV/rv64zbkb.ll
index c86f720818b0..6aabf78374ea 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbkb.ll
@@ -41,6 +41,28 @@ define signext i32 @pack_i32_2(i16 zeroext %a, i16 zeroext %b) nounwind {
   ret i32 %or
 }
 
+; Test case where we don't have a sign_extend_inreg after the or.
+define signext i32 @pack_i32_3(i16 zeroext %0, i16 zeroext %1, i32 signext %2) {
+; RV64I-LABEL: pack_i32_3:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 16
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    addw a0, a0, a2
+; RV64I-NEXT:    ret
+;
+; RV64ZBKB-LABEL: pack_i32_3:
+; RV64ZBKB:       # %bb.0:
+; RV64ZBKB-NEXT:    packw a0, a1, a0
+; RV64ZBKB-NEXT:    addw a0, a0, a2
+; RV64ZBKB-NEXT:    ret
+  %4 = zext i16 %0 to i32
+  %5 = shl nuw i32 %4, 16
+  %6 = zext i16 %1 to i32
+  %7 = or i32 %5, %6
+  %8 = add i32 %7, %2
+  ret i32 %8
+}
+
 define i64 @pack_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: pack_i64:
 ; RV64I:       # %bb.0: