[llvm] 03f9009 - [RISCV] Fix incorrect early out from isSignExtendedW in RISCVSExtWRemoval.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-11-13T17:30:39-08:00
New Revision: 03f9009cbf2a94c65692c209f091b1d63b37c991

URL: https://github.com/llvm/llvm-project/commit/03f9009cbf2a94c65692c209f091b1d63b37c991
DIFF: https://github.com/llvm/llvm-project/commit/03f9009cbf2a94c65692c209f091b1d63b37c991.diff

LOG: [RISCV] Fix incorrect early out from isSignExtendedW in RISCVSExtWRemoval.

We can only return false to abort. If the criteria is met we need
to use continue instead. Returning true stops us from visiting all
nodes and makes the caller think it is safe to remove sext.w.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
    llvm/test/CodeGen/RISCV/sextw-removal.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
index 62154c737da0..8a6c728e1734 100644
--- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -343,7 +343,7 @@ static bool isSignExtendedW(MachineInstr &OrigMI, MachineRegisterInfo &MRI,
     if (isSignExtendingOpW(*MI, MRI, FixableDef))
       continue;
 
-    // Is this an instruction that propagates sign extend.
+    // Is this an instruction that propagates sign extend?
     switch (MI->getOpcode()) {
     default:
       // Unknown opcode, give up.
@@ -357,8 +357,8 @@ static bool isSignExtendedW(MachineInstr &OrigMI, MachineRegisterInfo &MRI,
       // it is sign extended.
       if (MI->getParent() == &MF->front()) {
         Register VReg = MI->getOperand(0).getReg();
-        if (MF->getRegInfo().isLiveIn(VReg))
-          return RVFI->isSExt32Register(VReg);
+        if (MF->getRegInfo().isLiveIn(VReg) && RVFI->isSExt32Register(VReg))
+          continue;
       }
 
       // TODO: Handle returns from calls?

diff  --git a/llvm/test/CodeGen/RISCV/sextw-removal.ll b/llvm/test/CodeGen/RISCV/sextw-removal.ll
index 5dada972b86a..963fe7c7d985 100644
--- a/llvm/test/CodeGen/RISCV/sextw-removal.ll
+++ b/llvm/test/CodeGen/RISCV/sextw-removal.ll
@@ -1020,7 +1020,7 @@ bb7:                                              ; preds = %bb2
   ret i32 %i7
 }
 
-; FIXME: This test removes a sext.w without converting a slli to slliw.
+; This test previously removed a sext.w without converting a slli to slliw.
 define signext i32 @bug(i32 signext %x) {
 ; CHECK-LABEL: bug:
 ; CHECK:       # %bb.0: # %entry
@@ -1063,7 +1063,7 @@ define signext i32 @bug(i32 signext %x) {
 ; CHECK-NEXT:    srliw a2, a0, 30
 ; CHECK-NEXT:    bnez a2, .LBB18_7
 ; CHECK-NEXT:  .LBB18_12:
-; CHECK-NEXT:    slli a0, a0, 2
+; CHECK-NEXT:    slliw a0, a0, 2
 ; CHECK-NEXT:    beqz a2, .LBB18_8
 ; CHECK-NEXT:    j .LBB18_9
 ;