[PATCH] D137886: [RISCV] Add isel patterns to select slli+shXadd.uw.

[Craig Topper via Phabricator via llvm-commits]

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This matches what we get for something like.
%0 = shl i32 %x, C
%1 = zext i32 %0 to i64
%2 = getelementptr i32, ptr %y, %1

The shift before the zext and the shift implied by the GEP get
combined with an AND after them. We need to split it back into
2 shifts so we can fold one into shXadd.uw.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137886

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/test/CodeGen/RISCV/rv64zba.ll

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