[llvm] 57dbca2 - Revert "[Hexagon] Use default attributes for intrinsics"

[Alina Sbirlea via llvm-commits]

Author: Alina Sbirlea
Date: 2022-11-11T15:10:05-08:00
New Revision: 57dbca20eae8db0fd17cc59fe98c7804f02d6644

URL: https://github.com/llvm/llvm-project/commit/57dbca20eae8db0fd17cc59fe98c7804f02d6644
DIFF: https://github.com/llvm/llvm-project/commit/57dbca20eae8db0fd17cc59fe98c7804f02d6644.diff

LOG: Revert "[Hexagon] Use default attributes for intrinsics"

This reverts commit 8a8983b279dd5e4dceabe1fadbb8980b6adb88f9.

Uncovers existing regalloc issue in Hexagon backend - blocking for Halide
Hexagon users. Reverting to unblock, to be recommitted when underlying issue is resolved.
Reproducer available shortly.

Added: 
    

Modified: 
    llvm/include/llvm/IR/IntrinsicsHexagon.td
    llvm/test/CodeGen/Hexagon/circ-load-isel.ll
    llvm/test/CodeGen/Hexagon/select-vector-pred.ll

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/IR/IntrinsicsHexagon.td b/llvm/include/llvm/IR/IntrinsicsHexagon.td
index 847197ce28b93..9c7c43144db5a 100644
--- a/llvm/include/llvm/IR/IntrinsicsHexagon.td
+++ b/llvm/include/llvm/IR/IntrinsicsHexagon.td
@@ -19,14 +19,14 @@ let TargetPrefix = "hexagon" in {
                               list<LLVMType> param_types,
                               list<IntrinsicProperty> properties>
     : ClangBuiltin<!strconcat("__builtin_", GCCIntSuffix)>,
-      DefaultAttrsIntrinsic<ret_types, param_types, properties>;
+      Intrinsic<ret_types, param_types, properties>;
 
   /// Hexagon_NonGCC_Intrinsic - Base class for bitcode convertible Hexagon
   /// intrinsics.
   class Hexagon_NonGCC_Intrinsic<list<LLVMType> ret_types,
                                  list<LLVMType> param_types,
                                  list<IntrinsicProperty> properties>
-    : DefaultAttrsIntrinsic<ret_types, param_types, properties>;
+    : Intrinsic<ret_types, param_types, properties>;
 }
 
 class Hexagon_mem_memmemsi_Intrinsic<string GCCIntSuffix>
@@ -129,27 +129,19 @@ def llvm_ptr32_ty : LLVMPointerType<llvm_i32_ty>;
 def llvm_ptr64_ty : LLVMPointerType<llvm_i64_ty>;
 
 // Mark locked loads as read/write to prevent any accidental reordering.
-// These don't use Hexagon_Intrinsic, because they are not nosync, and as such
-// cannot use default attributes.
-let TargetPrefix = "hexagon" in {
-  def int_hexagon_L2_loadw_locked :
-  ClangBuiltin<"__builtin_HEXAGON_L2_loadw_locked">,
-  Intrinsic<[llvm_i32_ty], [llvm_ptr32_ty],
-        [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
-  def int_hexagon_L4_loadd_locked :
-  ClangBuiltin<"__builtin__HEXAGON_L4_loadd_locked">,
-  Intrinsic<[llvm_i64_ty], [llvm_ptr64_ty],
-        [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
-
-  def int_hexagon_S2_storew_locked :
-  ClangBuiltin<"__builtin_HEXAGON_S2_storew_locked">,
-  Intrinsic<[llvm_i32_ty],
-        [llvm_ptr32_ty, llvm_i32_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
-  def int_hexagon_S4_stored_locked :
-  ClangBuiltin<"__builtin_HEXAGON_S4_stored_locked">,
-  Intrinsic<[llvm_i32_ty],
-        [llvm_ptr64_ty, llvm_i64_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
-}
+def int_hexagon_L2_loadw_locked :
+Hexagon_Intrinsic<"HEXAGON_L2_loadw_locked", [llvm_i32_ty], [llvm_ptr32_ty],
+      [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
+def int_hexagon_L4_loadd_locked :
+Hexagon_Intrinsic<"HEXAGON_L4_loadd_locked", [llvm_i64_ty], [llvm_ptr64_ty],
+      [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
+
+def int_hexagon_S2_storew_locked :
+Hexagon_Intrinsic<"HEXAGON_S2_storew_locked", [llvm_i32_ty],
+      [llvm_ptr32_ty, llvm_i32_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
+def int_hexagon_S4_stored_locked :
+Hexagon_Intrinsic<"HEXAGON_S4_stored_locked", [llvm_i32_ty],
+      [llvm_ptr64_ty, llvm_i64_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
 
 def int_hexagon_vmemcpy : Hexagon_Intrinsic<"hexagon_vmemcpy",
     [], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty],

diff  --git a/llvm/test/CodeGen/Hexagon/circ-load-isel.ll b/llvm/test/CodeGen/Hexagon/circ-load-isel.ll
index dd343a3fdf1c8..576fbdf53cfc3 100644
--- a/llvm/test/CodeGen/Hexagon/circ-load-isel.ll
+++ b/llvm/test/CodeGen/Hexagon/circ-load-isel.ll
@@ -10,7 +10,7 @@ define void @circ2() #0 {
 entry:
   store i32 0, i32* @l, align 4
   %0 = tail call i8* @llvm.hexagon.circ.ldw(i8* undef, i8* undef, i32 150995968, i32 4)
-  ret void
+  unreachable
 }
 
 declare i8* @llvm.hexagon.circ.ldw(i8*, i8*, i32, i32) #1

diff  --git a/llvm/test/CodeGen/Hexagon/select-vector-pred.ll b/llvm/test/CodeGen/Hexagon/select-vector-pred.ll
index 4c5c0886f8008..58a052cc37012 100644
--- a/llvm/test/CodeGen/Hexagon/select-vector-pred.ll
+++ b/llvm/test/CodeGen/Hexagon/select-vector-pred.ll
@@ -21,8 +21,8 @@ entry:
   %3 = tail call <128 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32 %.sroa.speculated.i13.i.i) #3
   %4 = tail call <128 x i1> @llvm.hexagon.V6.pred.and.128B(<128 x i1> undef, <128 x i1> %3) #3
   tail call void @llvm.hexagon.V6.vS32b.qpred.ai.128B(<128 x i1> %4, i8* nonnull undef, <32 x i32> undef) #3
-  ret void
-}
+  unreachable
+                  }
 
 attributes #0 = { nounwind writeonly }
 attributes #1 = { nounwind readnone }