[PATCH] D137856: [RISCV] Reduce VL of splat instructions used to feed stores

[Philip Reames via Phabricator via llvm-commits]

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If we splat a value into N lanes, and then the only use of the resulting vector is a store of M lanes, we can reduce the size of the splat to min(M,N).  Lanes between M and N (if M < N) can't be observed.

In principle, reducing the width of the splat could cause an additional VL toggle, but this appears not to happen much in practice.

This is a carved down version D130895 <https://reviews.llvm.org/D130895>.  The intention of this patch is to provide a base from which complexity of that patch can be added upon with incremental review.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137856

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

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