[PATCH] D137530: [RISCV] Splat scalar to be of length VL instead of 1 for reductions

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

Comment inline with a problematic case.

Note as well that InsertVSETVLI should already be eliding the vsetvli when we can prove the avl non-zero.



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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll:12
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
-; CHECK-NEXT:    vfmv.s.f v9, fa0
-; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma
+; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT:    vfmv.v.f v9, fa0
----------------
There's a subtle semantic distinction between the old and proposed code here where a0 is zero.  

The old code would unconditionally insert the neutral element into v9, and then the vfredusum would see a VL=0, and not update the destination register.  As a result, the final return value is the neutral element.

The new code leaves v9 unchanged, and thus the result is whatever lane 0 of the v9 register happened to contain previously.


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  https://reviews.llvm.org/D137530/new/

https://reviews.llvm.org/D137530