[PATCH] D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically

[Haohai, Wen via Phabricator via llvm-commits]

HaohaiWen added a comment.



>   def ADLPWriteResGroup222 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05]> {
>     let ResourceCycles = [2, 2, 1, 2];
>     let Latency = 6;
>     let NumMicroOps = 7;
>   }
>   def : InstRW<[ADLPWriteResGroup222], (instregex "^SHA1MSG2rr$")>;
>
> That could just as well be (instrs SHA1MSG2rr)

Fixed


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D130897/new/

https://reviews.llvm.org/D130897