[llvm] bd27ac4 - Precommit for redundant and after SVE load

[Matt Devereau via llvm-commits]

Author: Benjamin Maxwell
Date: 2022-11-11T15:29:04Z
New Revision: bd27ac42988873cc102626b029de953d9797847b

URL: https://github.com/llvm/llvm-project/commit/bd27ac42988873cc102626b029de953d9797847b
DIFF: https://github.com/llvm/llvm-project/commit/bd27ac42988873cc102626b029de953d9797847b.diff

LOG: Precommit for redundant and after SVE load

Added: 
    llvm/test/CodeGen/AArch64/sve-load-compare-store.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AArch64/sve-load-compare-store.ll b/llvm/test/CodeGen/AArch64/sve-load-compare-store.ll
new file mode 100644
index 000000000000..27436ede52eb
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-load-compare-store.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s
+
+define void @sve_load_compare_store(ptr noalias nocapture noundef readonly %a, ptr noalias nocapture noundef %b) {
+; CHECK-LABEL: sve_load_compare_store:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ptrue p0.b
+; CHECK-NEXT:    ld1h { z0.s }, p0/z, [x0]
+; CHECK-NEXT:    mov z1.d, z0.d
+; CHECK-NEXT:    and z1.s, z1.s, #0xffff
+; CHECK-NEXT:    cmphs p0.s, p0/z, z1.s, #0
+; CHECK-NEXT:    st1b { z0.s }, p0, [x1]
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
+  %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %0)
+  %2 = tail call <vscale x 4 x i16> @llvm.masked.load.nxv4i16.p0(ptr %a, i32 1, <vscale x 4 x i1> %1, <vscale x 4 x i16> zeroinitializer)
+  %3 = zext <vscale x 4 x i16> %2 to <vscale x 4 x i32>
+  %4 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %3, <vscale x 4 x i32> zeroinitializer)
+  %5 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %4)
+  %6 = trunc <vscale x 4 x i16> %2 to <vscale x 4 x i8>
+  tail call void @llvm.masked.store.nxv4i8.p0(<vscale x 4 x i8> %6, ptr %b, i32 1, <vscale x 4 x i1> %4)
+  ret void
+}
+
+declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg)
+declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>)
+declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphs.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>)
+declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
+declare <vscale x 4 x i16> @llvm.masked.load.nxv4i16.p0(ptr, i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i16>)
+declare void @llvm.masked.store.nxv4i8.p0(<vscale x 4 x i8>, ptr, i32 immarg, <vscale x 4 x i1>)