[llvm] 2116d69 - [X86] Replace unnecessary CVTPS2DQ folded overrides with better base class defs

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-11-11T14:51:05Z
New Revision: 2116d69f100c243069be1e76ac7fdac65ea5328a

URL: https://github.com/llvm/llvm-project/commit/2116d69f100c243069be1e76ac7fdac65ea5328a
DIFF: https://github.com/llvm/llvm-project/commit/2116d69f100c243069be1e76ac7fdac65ea5328a.diff

LOG: [X86] Replace unnecessary CVTPS2DQ folded overrides with better base class defs

Broadwell just needed the load latency to be tweaked for the overrides to be unnecessary - I think this was due to Issue #38536 (underestimation of most broadwell load latencies)

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86SchedBroadwell.td
    llvm/lib/Target/X86/X86SchedHaswell.td

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index 7156c2ea9d592..0040d0e4f2dc3 100644
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -358,8 +358,8 @@ defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
 
 // Conversion between integer and float.
 defm : BWWriteResPair<WriteCvtSS2I,   [BWPort1,BWPort0], 4, [1,1], 2, 5>;
-defm : BWWriteResPair<WriteCvtPS2I,   [BWPort1], 3>;
-defm : BWWriteResPair<WriteCvtPS2IY,  [BWPort1], 3>;
+defm : BWWriteResPair<WriteCvtPS2I,   [BWPort1], 3, [1], 1, 5>;
+defm : BWWriteResPair<WriteCvtPS2IY,  [BWPort1], 3, [1], 1, 6>;
 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
 defm : BWWriteResPair<WriteCvtSD2I,   [BWPort1,BWPort0], 4, [1,1], 2, 5>;
 defm : BWWriteResPair<WriteCvtPD2I,   [BWPort1,BWPort5], 4, [1,1], 2, 5>;
@@ -1175,8 +1175,6 @@ def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
 }
 def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
                                              "ILD_F(16|32|64)m")>;
-def: InstRW<[BWWriteResGroup101], (instrs VCVTPS2DQYrm,
-                                          VCVTTPS2DQYrm)>;
 
 def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
   let Latency = 9;

diff  --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index 7c5804fc198f2..c0c38263b82bc 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -1234,14 +1234,6 @@ def HWWriteResGroup51 : SchedWriteRes<[HWPort5]> {
 }
 def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCAST(B|W)rr")>;
 
-def HWWriteResGroup52 : SchedWriteRes<[HWPort1,HWPort23]> {
-  let Latency = 9;
-  let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
-}
-def: InstRW<[HWWriteResGroup52], (instregex "(V?)CVTPS2DQrm",
-                                            "(V?)CVTTPS2DQrm")>;
-
 def HWWriteResGroup52_1 : SchedWriteRes<[HWPort1,HWPort23]> {
   let Latency = 10;
   let NumMicroOps = 2;
@@ -1249,8 +1241,6 @@ def HWWriteResGroup52_1 : SchedWriteRes<[HWPort1,HWPort23]> {
 }
 def: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
                                               "ILD_F(16|32|64)m")>;
-def: InstRW<[HWWriteResGroup52_1], (instrs VCVTPS2DQYrm,
-                                           VCVTTPS2DQYrm)>;
 
 def HWWriteResGroup53_1 : SchedWriteRes<[HWPort5,HWPort23]> {
   let Latency = 9;