[PATCH] D134423: [AMDGPU] Fix vgpr2sgpr copy analysis to check scalar operands of buffer instructions use scalar registers.

Thu Nov 10 10:15:11 PST 2022

alex-t added a comment.

In D134423#3914502 <https://reviews.llvm.org/D134423#3914502>, @foad wrote:

> In D134423#3912577 <https://reviews.llvm.org/D134423#3912577>, @alex-t wrote:
>
>> BTW, if %5 is divergent we have a bug in ISel. We now should not have any V2S copy with the divergent source.
>
> Look at the MIR that @skc7 quoted. %5 is divergent - it's copied from a vgpr function argument.

The BUFFER_LOAD_DWORDX4_OFFEN is one of (as I remember correctly 5) the exceptional opcodes for which V2S copy is created even in case the copy source is divergent.
There is no bug in ISel. We have the value in VGPR because it is divergent and this is correct. The V2S copy is created in InstrEmitter just because the opcode requires SGPR.
We have yet several other such opcodes. And this is really a TODO.

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https://reviews.llvm.org/D134423