[PATCH] D136663: Handling ADD|SUB U64 decomposed Pseudos not getting lowered to SDWA form

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

Looks good overall.



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Comment at: llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp:902
 
-  // Replace MISucc with V_{SUBB|ADDC}_U32_e32
-  BuildMI(MBB, MISucc, MISucc.getDebugLoc(), TII->get(SuccOpc))
-    .add(*TII->getNamedOperand(MISucc, AMDGPU::OpName::vdst))
-    .add(*TII->getNamedOperand(MISucc, AMDGPU::OpName::src0))
-    .add(*TII->getNamedOperand(MISucc, AMDGPU::OpName::src1))
-    .setMIFlags(MISucc.getFlags());
+  // Since the carry outpur of MI is now VCC, update it's use in MISucc
 
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"output", "its" (no apostrophe), full stop at end of sentence.


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Comment at: llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp:904
 
-  MISucc.eraseFromParent();
+  MISucc.substituteRegister(CarryIn->getReg(), AMDGPU::VCC, 0, *TRI);
 }
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Doesn't this need to be VCC_LO for wave32? Please add a test for that. You can use SIRegisterInfo::getVCC() to get the appropriate reg for the wave size.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D136663/new/

https://reviews.llvm.org/D136663