[PATCH] D136858: [AArch64-SVE]: Force generating code compatible to streaming mode for sve-fixed-length tests.

[hassnaaHamdi via Phabricator via llvm-commits]

hassnaa-arm added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll:321
+
+define void @fcvtzu_v16f32_v16i16(<16 x float>* %a, <16 x i16>* %b) #0 {
+; CHECK-LABEL: fcvtzu_v16f32_v16i16:
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david-arm wrote:
> I think we can remove this test because the input vector > 256 bits.
I left it because the output vector is not > 256.
So, for all cases, I leave it if one of the intput/output vector is not > 256


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Comment at: llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll:1070
+
+define void @fcvtzs_v16f32_v16i16(<16 x float>* %a, <16 x i16>* %b) #0 {
+; CHECK-LABEL: fcvtzs_v16f32_v16i16:
----------------
david-arm wrote:
> Remove this test, since input > 256 bits?
I left it because the output vector is not > 256.
So, for all cases, I leave it if one of the intput/output vector is not > 256


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136858/new/

https://reviews.llvm.org/D136858