[llvm] 1ef2a92 - [PowerPC] Add the SUBFUS instruction to Future CPU.
Stefan Pintilie via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 10 06:32:35 PST 2022
Author: Stefan Pintilie
Date: 2022-11-10T08:32:29-06:00
New Revision: 1ef2a92d6679af7ddeaf20d4e0304f1cd22f28bb
URL: https://github.com/llvm/llvm-project/commit/1ef2a92d6679af7ddeaf20d4e0304f1cd22f28bb
DIFF: https://github.com/llvm/llvm-project/commit/1ef2a92d6679af7ddeaf20d4e0304f1cd22f28bb.diff
LOG: [PowerPC] Add the SUBFUS instruction to Future CPU.
Add a new instruction called SUBUFS that does saturating subtract.
This instruction is only for Future CPU.
Reviewed By: amyk
Differential Revision: https://reviews.llvm.org/D137643
Added:
Modified:
llvm/lib/Target/PowerPC/PPCInstrFuture.td
llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 63b77e46f01f4..0d3ac801f20eb 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -11,4 +11,43 @@
//
//===----------------------------------------------------------------------===//
+class XOForm_RTAB5_L1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
+ string asmstr, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+ bits<5> RT;
+ bits<5> RA;
+ bits<5> RB;
+ bit L;
+
+ let Pattern = pattern;
+
+ bit RC = 0; // set by isRecordForm
+
+ let Inst{6-10} = RT;
+ let Inst{11-15} = RA;
+ let Inst{16-20} = RB;
+ let Inst{21} = L;
+ let Inst{22-30} = xo;
+ let Inst{31} = RC;
+}
+
+multiclass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
+ string asmbase, string asmstr,
+ list<dag> pattern> {
+ let BaseName = asmbase in {
+ def NAME : XOForm_RTAB5_L1<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(" ", asmstr)),
+ pattern>, RecFormRel;
+ let Defs = [CR0] in
+ def _rec : XOForm_RTAB5_L1<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(". ", asmstr)),
+ []>, isRecordForm, RecFormRel;
+ }
+}
+
+let Predicates = [IsISAFuture] in {
+defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
+ (ins g8rc:$RA, g8rc:$RB, u1imm:$L),
+ "subfus", "$RT, $L, $RA, $RB", []>;
+}
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
index 87059b9e3c16c..ceca437b3b88b 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
@@ -39,3 +39,15 @@
#CHECK: dmxor 6, 7
0x7f 0x07 0xe1 0x62
+
+#CHECK: subfus 3, 0, 4, 5
+0x7c 0x64 0x28 0x90
+
+#CHECK: subfus 3, 1, 4, 5
+0x7c 0x64 0x2c 0x90
+
+#CHECK: subfus. 3, 0, 4, 5
+0x7c 0x64 0x28 0x91
+
+#CHECK: subfus. 3, 1, 4, 5
+0x7c 0x64 0x2c 0x91
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
index 32dfcb28bf57c..60528881125e0 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
@@ -33,3 +33,15 @@
#CHECK: dmxor 6, 7
0x62 0xe1 0x07 0x7f
+
+#CHECK: subfus 3, 0, 4, 5
+0x90 0x28 0x64 0x7c
+
+#CHECK: subfus 3, 1, 4, 5
+0x90 0x2c 0x64 0x7c
+
+#CHECK: subfus. 3, 0, 4, 5
+0x91 0x28 0x64 0x7c
+
+#CHECK: subfus. 3, 1, 4, 5
+0x91 0x2c 0x64 0x7c
diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
index 2f7986f221c97..192a570df8f31 100644
--- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
+++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
@@ -48,3 +48,19 @@
# CHECK-BE: dmxor 6, 7 # encoding: [0x7f,0x07,0xe1,0x62]
# CHECK-LE: dmxor 6, 7 # encoding: [0x62,0xe1,0x07,0x7f]
dmxor 6, 7
+
+# CHECK-BE: subfus 3, 0, 4, 5 # encoding: [0x7c,0x64,0x28,0x90]
+# CHECK-LE: subfus 3, 0, 4, 5 # encoding: [0x90,0x28,0x64,0x7c]
+ subfus 3, 0, 4, 5
+
+# CHECK-BE: subfus 3, 1, 4, 5 # encoding: [0x7c,0x64,0x2c,0x90]
+# CHECK-LE: subfus 3, 1, 4, 5 # encoding: [0x90,0x2c,0x64,0x7c]
+ subfus 3, 1, 4, 5
+
+# CHECK-BE: subfus. 3, 0, 4, 5 # encoding: [0x7c,0x64,0x28,0x91]
+# CHECK-LE: subfus. 3, 0, 4, 5 # encoding: [0x91,0x28,0x64,0x7c]
+ subfus. 3, 0, 4, 5
+
+# CHECK-BE: subfus. 3, 1, 4, 5 # encoding: [0x7c,0x64,0x2c,0x91]
+# CHECK-LE: subfus. 3, 1, 4, 5 # encoding: [0x91,0x2c,0x64,0x7c]
+ subfus. 3, 1, 4, 5
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