[PATCH] D137783: [AMDGPU][MC] Support TFE modifiers in MUBUF loads and stores.

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev added a comment.

The most of the changes are for tests where the presence of the TFE operands doesn't make much sense and the code changes seem compact enough to not bother with making non-existing instructions possible and then slashing them with custom checks as we do for MIMGs. Also agrees with the existing practice of having the LDS and Offset/Index/Both variants as separate instructions.

For some reason SP3 additionally accepts TFE forms with vN VData operands where v[N:N+1] is expected, so for example `buffer_load_dword v1, v0, s[4:7], s1 glc tfe` and `buffer_load_dword v[1:2], v0, s[4:7], s1 glc tfe` are both accepted and produce same opcodes. It should be possible to support that with a separate change, if needed.

Apart from that, https://reviews.llvm.org/D19584 mentions that use of `off` operands agrees with SP3. I wasn't able to find any signs in SP3 behaviour confirming this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137783/new/

https://reviews.llvm.org/D137783