[PATCH] D136172: [AArch64]SME2 Multi vector Sel Load and Store instructions

Caroline via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Nov 10 03:53:55 PST 2022


CarolineConcatto added inline comments.


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:3841-3842
+   let Inst{4}     = Zt{2};
+   let Inst{3}     = n;
+   let Inst{1-0}   = Zt{1-0};
+
----------------
paulwalker-arm wrote:
> This is missing `let Inst{2} = 0b0;`.
Thank you Paul! I would have thought the build would have shown that, specially the encoding test.
I think that if we don't set the value it becomes zero.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136172/new/

https://reviews.llvm.org/D136172



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