[PATCH] D137721: [AArch64] Optimize more memcmp when the result is tested for [in]equality with 0

[Allen zhong via Phabricator via llvm-commits]

Allen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:8553
+  // The leaf node must be XOR
+  if (N->getOpcode() == ISD::XOR) {
+    WorkList.push_back(std::make_pair(N->getOperand(0), N->getOperand(1)));
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bcl5980 wrote:
> Can ISD::SUB be leaf node also?
Thanks, But I doesn't sure this need be extended as the bcmp doesn't generate such IR after outlining?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:8559
+  // All the non-leaf nodes must be OR.
+  if (N->getOpcode() != ISD::OR)
+    return false;
----------------
bcl5980 wrote:
> Do we need add one-use check for `or`? 
> Or generate the depth of the node to determine the more than one use node can enable the opt or not?
Yes, we can check the one-use to start, thanks.
If more complex scenarios are required in the actual code, then the depth may also need later.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:8580
+  // Try to express conjunction "cmp 0 (or (xor A0 A1) (xor B0 B1))" as:
+  // cmp A0, A0; ccmp A0, B1, 0, eq; cmp inv(Cond) flag
+  if (VT.isScalarInteger() && (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
----------------
bcl5980 wrote:
> `cmp A0, A1; ccmp B0, B1` ?
Done, thanks!


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137721/new/

https://reviews.llvm.org/D137721