[PATCH] D137427: [RISCV][Codegen] Account for LMUL in Vector Mask instructions
Kito Cheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 9 22:30:17 PST 2022
kito-cheng added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:832
-// 16. Vector Mask Instructions
-def : ReadAdvance<ReadVMALUV, 0>;
-def : ReadAdvance<ReadVMPopV, 0>;
-def : ReadAdvance<ReadVMFFSV, 0>;
-def : ReadAdvance<ReadVMSFSV, 0>;
-def : ReadAdvance<ReadVMIotV, 0>;
+// 15. Vector Mask Instructions
+defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
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I think that could be fixed in another small document fix only NFC patch?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D137427/new/
https://reviews.llvm.org/D137427
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