[PATCH] D137612: [PowerPC] add a new subtarget feature FastMFLR

[ChenZheng via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG454758ab6931: [PowerPC] add a new subtarget feature fastMFLR (authored by shchenz).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137612/new/

https://reviews.llvm.org/D137612

Files:
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h


Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===================================================================
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -168,6 +168,7 @@
   bool UsePPCPostRASchedStrategy;
   bool PairedVectorMemops;
   bool PredictableSelectIsExpensive;
+  bool HasFastMFLR;
   bool HasModernAIXAs;
   bool IsAIX;
 
@@ -316,6 +317,7 @@
   bool hasPartwordAtomics() const { return HasPartwordAtomics; }
   bool hasQuadwordAtomics() const { return HasQuadwordAtomics; }
   bool hasDirectMove() const { return HasDirectMove; }
+  bool hasFastMFLR() const { return HasFastMFLR; }
 
   Align getPlatformStackAlignment() const {
     return Align(16);
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -149,6 +149,7 @@
   UsePPCPostRASchedStrategy = false;
   PairedVectorMemops = false;
   PredictableSelectIsExpensive = false;
+  HasFastMFLR = false;
   HasModernAIXAs = false;
   IsAIX = false;
 
Index: llvm/lib/Target/PowerPC/PPC.td
===================================================================
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -316,6 +316,9 @@
                    "true",
                    "Prefer likely predicted branches over selects">;
 
+def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true",
+                                       "MFLR is a fast instruction">;
+
 // Since new processors generally contain a superset of features of those that
 // came before them, the idea is to make implementations of new processors
 // less error prone and easier to read.
@@ -424,7 +427,7 @@
     !listconcat(FusionFeatures, [
        DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
        FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA,
-       FeaturePairedVectorMemops]);
+       FeaturePairedVectorMemops, FeatureFastMFLR]);
   list<SubtargetFeature> P10SpecificFeatures = [];
   list<SubtargetFeature> P10InheritableFeatures =
     !listconcat(P9InheritableFeatures, P10AdditionalFeatures);


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D137612.474427.patch
Type: text/x-patch
Size: 2198 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221110/2b6e1033/attachment.bin>