[llvm] 454758a - [PowerPC] add a new subtarget feature fastMFLR

[Chen Zheng via llvm-commits]

Author: Chen Zheng
Date: 2022-11-10T00:07:47-05:00
New Revision: 454758ab69315e4e20f5cb0746535f7665dbcfe4

URL: https://github.com/llvm/llvm-project/commit/454758ab69315e4e20f5cb0746535f7665dbcfe4
DIFF: https://github.com/llvm/llvm-project/commit/454758ab69315e4e20f5cb0746535f7665dbcfe4.diff

LOG: [PowerPC] add a new subtarget feature fastMFLR

Some PowerPC CPU may have slow MFLR instruction, so we need to
schedule the MFLR and its store in function prologue away to
hidden the long latency for slow MFLR instruction.

This patch adds a new feature fastMFLR and the new feature will
be used in https://reviews.llvm.org/D137423.

Reviewed By: RolandF

Differential Revision: https://reviews.llvm.org/D137612

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPC.td
    llvm/lib/Target/PowerPC/PPCSubtarget.cpp
    llvm/lib/Target/PowerPC/PPCSubtarget.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index c231bb4069d23..53f930bebce74 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -316,6 +316,9 @@ def FeaturePredictableSelectIsExpensive :
                    "true",
                    "Prefer likely predicted branches over selects">;
 
+def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true",
+                                       "MFLR is a fast instruction">;
+
 // Since new processors generally contain a superset of features of those that
 // came before them, the idea is to make implementations of new processors
 // less error prone and easier to read.
@@ -424,7 +427,7 @@ def ProcessorFeatures {
     !listconcat(FusionFeatures, [
        DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
        FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA,
-       FeaturePairedVectorMemops]);
+       FeaturePairedVectorMemops, FeatureFastMFLR]);
   list<SubtargetFeature> P10SpecificFeatures = [];
   list<SubtargetFeature> P10InheritableFeatures =
     !listconcat(P9InheritableFeatures, P10AdditionalFeatures);

diff  --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
index 98424234a592e..599629c6fb2b0 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -149,6 +149,7 @@ void PPCSubtarget::initializeEnvironment() {
   UsePPCPostRASchedStrategy = false;
   PairedVectorMemops = false;
   PredictableSelectIsExpensive = false;
+  HasFastMFLR = false;
   HasModernAIXAs = false;
   IsAIX = false;
 

diff  --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h
index 3281816eab4af..6df96312670d8 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -168,6 +168,7 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
   bool UsePPCPostRASchedStrategy;
   bool PairedVectorMemops;
   bool PredictableSelectIsExpensive;
+  bool HasFastMFLR;
   bool HasModernAIXAs;
   bool IsAIX;
 
@@ -316,6 +317,7 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
   bool hasPartwordAtomics() const { return HasPartwordAtomics; }
   bool hasQuadwordAtomics() const { return HasQuadwordAtomics; }
   bool hasDirectMove() const { return HasDirectMove; }
+  bool hasFastMFLR() const { return HasFastMFLR; }
 
   Align getPlatformStackAlignment() const {
     return Align(16);