[PATCH] D134711: [AArch64] Select SMULL for zero extended vectors when top bit is zero

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.

Thanks. A small nit, but otherwise this looks like a good patch. The newly created node will never be used, but I don't think that would be a problem. LGTM



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:4407
+  }
   if (IsN0ZExt && IsN1ZExt)
     return AArch64ISD::UMULL;
----------------
Small nit but can you move this above the new code? This condition and the new one are mutually exclusive, and it would seem a little better to have the check for two zext next to the `bool IsN0ZExt = ...`, the same as the base smull case.


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https://reviews.llvm.org/D134711