[llvm] 835de8d - [AArch64][SVE2] Add the SVE2.1 integer quadword reduction instructions
David Sherwood via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 9 06:26:35 PST 2022
Author: David Sherwood
Date: 2022-11-09T14:26:23Z
New Revision: 835de8dcf1021de6d224625558346fd127358e08
URL: https://github.com/llvm/llvm-project/commit/835de8dcf1021de6d224625558346fd127358e08
DIFF: https://github.com/llvm/llvm-project/commit/835de8dcf1021de6d224625558346fd127358e08.diff
LOG: [AArch64][SVE2] Add the SVE2.1 integer quadword reduction instructions
This patch adds the assembly/disassembly for the following instructions:
addqv : Unsigned add reduction of quadword vector segments
andqv : Bitwise AND reduction of quadword vector segments
eorqv : Bitwise exclusive OR reduction of quadword vector segments
orqv : Bitwise inclusive OR reduction of quadword vector segments
smaxqv : Signed maximum reduction of quadword vector segments
sminqv : Signed minimum reduction of quadword vector segments
umaxqv : Unsigned maximum reduction of quadword vector segments
uminqv : Unsigned minimum reduction of quadword vector segments
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D137411
Added:
llvm/test/MC/AArch64/SVE2p1/addqv-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/addqv.s
llvm/test/MC/AArch64/SVE2p1/andqv-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/andqv.s
llvm/test/MC/AArch64/SVE2p1/eorqv-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/eorqv.s
llvm/test/MC/AArch64/SVE2p1/orqv-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/orqv.s
llvm/test/MC/AArch64/SVE2p1/smaxqv-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/smaxqv.s
llvm/test/MC/AArch64/SVE2p1/sminqv-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/sminqv.s
llvm/test/MC/AArch64/SVE2p1/umaxqv-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/umaxqv.s
llvm/test/MC/AArch64/SVE2p1/uminqv-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/uminqv.s
Modified:
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 8779ec5493c2..0abcbc3fb0a2 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -3784,4 +3784,13 @@ def EXTQ_ZZI : sve2p1_extq<"extq">;
defm PMOV_PZI : sve2p1_vector_to_pred<"pmov">;
defm PMOV_ZIP : sve2p1_pred_to_vector<"pmov">;
+
+defm ORQV_VPZ : sve2p1_int_reduce_q<0b1100, "orqv">;
+defm EORQV_VPZ : sve2p1_int_reduce_q<0b1101, "eorqv">;
+defm ANDQV_VPZ : sve2p1_int_reduce_q<0b1110, "andqv">;
+defm ADDQV_VPZ : sve2p1_int_reduce_q<0b0001, "addqv">;
+defm SMAXQV_VPZ : sve2p1_int_reduce_q<0b0100, "smaxqv">;
+defm UMAXQV_VPZ : sve2p1_int_reduce_q<0b0101, "umaxqv">;
+defm SMINQV_VPZ : sve2p1_int_reduce_q<0b0110, "sminqv">;
+defm UMINQV_VPZ : sve2p1_int_reduce_q<0b0111, "uminqv">;
} // End HasSVE2p1_or_HasSME2p1
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 31678ec92485..bf600f3d1982 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -9501,3 +9501,32 @@ multiclass sve2p1_pred_to_vector<string mnemonic> {
def : InstAlias<mnemonic # "\t$Zd, $Pn",
(!cast<Instruction>(NAME # _B) ZPRAny:$Zd, 0, PPR8:$Pn), 1>;
}
+
+
+// SVE bitwise logical/add/min/max reductions (quadwords)
+class sve2p1_int_reduce_q<bits<2> sz, bits<4> opc, string mnemonic,
+ RegisterOperand zpr_ty, string vec_sfx>
+ : I<(outs V128:$Vd), (ins PPR3bAny:$Pg, zpr_ty:$Zn),
+ mnemonic, "\t$Vd." # vec_sfx # ", $Pg, $Zn",
+ "", []>, Sched<[]> {
+ bits<5> Vd;
+ bits<5> Zn;
+ bits<3> Pg;
+ let Inst{31-24} = 0b00000100;
+ let Inst{23-22} = sz;
+ let Inst{21} = 0b0;
+ let Inst{20-19} = opc{3-2};
+ let Inst{18} = 0b1;
+ let Inst{17-16} = opc{1-0};
+ let Inst{15-13} = 0b001;
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Vd;
+}
+
+multiclass sve2p1_int_reduce_q<bits<4> opc, string mnemonic> {
+ def _B : sve2p1_int_reduce_q<0b00, opc, mnemonic, ZPR8, "16b">;
+ def _H : sve2p1_int_reduce_q<0b01, opc, mnemonic, ZPR16, "8h">;
+ def _S : sve2p1_int_reduce_q<0b10, opc, mnemonic, ZPR32, "4s">;
+ def _D : sve2p1_int_reduce_q<0b11, opc, mnemonic, ZPR64, "2d">;
+}
diff --git a/llvm/test/MC/AArch64/SVE2p1/addqv-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/addqv-diagnostics.s
new file mode 100644
index 000000000000..68c59c505900
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/addqv-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+addqv v0.2d, p11, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: addqv v0.2d, p11, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector register
+
+addqv v0.4h, p1, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: addqv v0.4h, p1, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+addqv z1.s, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: addqv z1.s, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+addqv v0.8h, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: addqv v0.8h, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/addqv.s b/llvm/test/MC/AArch64/SVE2p1/addqv.s
new file mode 100644
index 000000000000..98e469ee78ef
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/addqv.s
@@ -0,0 +1,110 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+addqv v0.8h, p0, z0.h // 00000100-01000101-00100000-00000000
+// CHECK-INST: addqv v0.8h, p0, z0.h
+// CHECK-ENCODING: [0x00,0x20,0x45,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04452000 <unknown>
+
+addqv v21.8h, p5, z10.h // 00000100-01000101-00110101-01010101
+// CHECK-INST: addqv v21.8h, p5, z10.h
+// CHECK-ENCODING: [0x55,0x35,0x45,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04453555 <unknown>
+
+addqv v23.8h, p3, z13.h // 00000100-01000101-00101101-10110111
+// CHECK-INST: addqv v23.8h, p3, z13.h
+// CHECK-ENCODING: [0xb7,0x2d,0x45,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04452db7 <unknown>
+
+addqv v31.8h, p7, z31.h // 00000100-01000101-00111111-11111111
+// CHECK-INST: addqv v31.8h, p7, z31.h
+// CHECK-ENCODING: [0xff,0x3f,0x45,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04453fff <unknown>
+
+addqv v0.4s, p0, z0.s // 00000100-10000101-00100000-00000000
+// CHECK-INST: addqv v0.4s, p0, z0.s
+// CHECK-ENCODING: [0x00,0x20,0x85,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04852000 <unknown>
+
+addqv v21.4s, p5, z10.s // 00000100-10000101-00110101-01010101
+// CHECK-INST: addqv v21.4s, p5, z10.s
+// CHECK-ENCODING: [0x55,0x35,0x85,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04853555 <unknown>
+
+addqv v23.4s, p3, z13.s // 00000100-10000101-00101101-10110111
+// CHECK-INST: addqv v23.4s, p3, z13.s
+// CHECK-ENCODING: [0xb7,0x2d,0x85,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04852db7 <unknown>
+
+addqv v31.4s, p7, z31.s // 00000100-10000101-00111111-11111111
+// CHECK-INST: addqv v31.4s, p7, z31.s
+// CHECK-ENCODING: [0xff,0x3f,0x85,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04853fff <unknown>
+
+addqv v0.2d, p0, z0.d // 00000100-11000101-00100000-00000000
+// CHECK-INST: addqv v0.2d, p0, z0.d
+// CHECK-ENCODING: [0x00,0x20,0xc5,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04c52000 <unknown>
+
+addqv v21.2d, p5, z10.d // 00000100-11000101-00110101-01010101
+// CHECK-INST: addqv v21.2d, p5, z10.d
+// CHECK-ENCODING: [0x55,0x35,0xc5,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04c53555 <unknown>
+
+addqv v23.2d, p3, z13.d // 00000100-11000101-00101101-10110111
+// CHECK-INST: addqv v23.2d, p3, z13.d
+// CHECK-ENCODING: [0xb7,0x2d,0xc5,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04c52db7 <unknown>
+
+addqv v31.2d, p7, z31.d // 00000100-11000101-00111111-11111111
+// CHECK-INST: addqv v31.2d, p7, z31.d
+// CHECK-ENCODING: [0xff,0x3f,0xc5,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04c53fff <unknown>
+
+addqv v0.16b, p0, z0.b // 00000100-00000101-00100000-00000000
+// CHECK-INST: addqv v0.16b, p0, z0.b
+// CHECK-ENCODING: [0x00,0x20,0x05,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04052000 <unknown>
+
+addqv v21.16b, p5, z10.b // 00000100-00000101-00110101-01010101
+// CHECK-INST: addqv v21.16b, p5, z10.b
+// CHECK-ENCODING: [0x55,0x35,0x05,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04053555 <unknown>
+
+addqv v23.16b, p3, z13.b // 00000100-00000101-00101101-10110111
+// CHECK-INST: addqv v23.16b, p3, z13.b
+// CHECK-ENCODING: [0xb7,0x2d,0x05,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04052db7 <unknown>
+
+addqv v31.16b, p7, z31.b // 00000100-00000101-00111111-11111111
+// CHECK-INST: addqv v31.16b, p7, z31.b
+// CHECK-ENCODING: [0xff,0x3f,0x05,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04053fff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/andqv-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/andqv-diagnostics.s
new file mode 100644
index 000000000000..6ca42109702f
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/andqv-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+andqv v0.2d, p11, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: andqv v0.2d, p11, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector register
+
+andqv v0.4h, p1, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: andqv v0.4h, p1, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+andqv z1.s, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: andqv z1.s, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+andqv v0.8h, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: andqv v0.8h, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/andqv.s b/llvm/test/MC/AArch64/SVE2p1/andqv.s
new file mode 100644
index 000000000000..38bce072961a
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/andqv.s
@@ -0,0 +1,110 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+andqv v0.8h, p0, z0.h // 00000100-01011110-00100000-00000000
+// CHECK-INST: andqv v0.8h, p0, z0.h
+// CHECK-ENCODING: [0x00,0x20,0x5e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 045e2000 <unknown>
+
+andqv v21.8h, p5, z10.h // 00000100-01011110-00110101-01010101
+// CHECK-INST: andqv v21.8h, p5, z10.h
+// CHECK-ENCODING: [0x55,0x35,0x5e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 045e3555 <unknown>
+
+andqv v23.8h, p3, z13.h // 00000100-01011110-00101101-10110111
+// CHECK-INST: andqv v23.8h, p3, z13.h
+// CHECK-ENCODING: [0xb7,0x2d,0x5e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 045e2db7 <unknown>
+
+andqv v31.8h, p7, z31.h // 00000100-01011110-00111111-11111111
+// CHECK-INST: andqv v31.8h, p7, z31.h
+// CHECK-ENCODING: [0xff,0x3f,0x5e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 045e3fff <unknown>
+
+andqv v0.4s, p0, z0.s // 00000100-10011110-00100000-00000000
+// CHECK-INST: andqv v0.4s, p0, z0.s
+// CHECK-ENCODING: [0x00,0x20,0x9e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 049e2000 <unknown>
+
+andqv v21.4s, p5, z10.s // 00000100-10011110-00110101-01010101
+// CHECK-INST: andqv v21.4s, p5, z10.s
+// CHECK-ENCODING: [0x55,0x35,0x9e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 049e3555 <unknown>
+
+andqv v23.4s, p3, z13.s // 00000100-10011110-00101101-10110111
+// CHECK-INST: andqv v23.4s, p3, z13.s
+// CHECK-ENCODING: [0xb7,0x2d,0x9e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 049e2db7 <unknown>
+
+andqv v31.4s, p7, z31.s // 00000100-10011110-00111111-11111111
+// CHECK-INST: andqv v31.4s, p7, z31.s
+// CHECK-ENCODING: [0xff,0x3f,0x9e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 049e3fff <unknown>
+
+andqv v0.2d, p0, z0.d // 00000100-11011110-00100000-00000000
+// CHECK-INST: andqv v0.2d, p0, z0.d
+// CHECK-ENCODING: [0x00,0x20,0xde,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04de2000 <unknown>
+
+andqv v21.2d, p5, z10.d // 00000100-11011110-00110101-01010101
+// CHECK-INST: andqv v21.2d, p5, z10.d
+// CHECK-ENCODING: [0x55,0x35,0xde,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04de3555 <unknown>
+
+andqv v23.2d, p3, z13.d // 00000100-11011110-00101101-10110111
+// CHECK-INST: andqv v23.2d, p3, z13.d
+// CHECK-ENCODING: [0xb7,0x2d,0xde,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04de2db7 <unknown>
+
+andqv v31.2d, p7, z31.d // 00000100-11011110-00111111-11111111
+// CHECK-INST: andqv v31.2d, p7, z31.d
+// CHECK-ENCODING: [0xff,0x3f,0xde,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04de3fff <unknown>
+
+andqv v0.16b, p0, z0.b // 00000100-00011110-00100000-00000000
+// CHECK-INST: andqv v0.16b, p0, z0.b
+// CHECK-ENCODING: [0x00,0x20,0x1e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 041e2000 <unknown>
+
+andqv v21.16b, p5, z10.b // 00000100-00011110-00110101-01010101
+// CHECK-INST: andqv v21.16b, p5, z10.b
+// CHECK-ENCODING: [0x55,0x35,0x1e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 041e3555 <unknown>
+
+andqv v23.16b, p3, z13.b // 00000100-00011110-00101101-10110111
+// CHECK-INST: andqv v23.16b, p3, z13.b
+// CHECK-ENCODING: [0xb7,0x2d,0x1e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 041e2db7 <unknown>
+
+andqv v31.16b, p7, z31.b // 00000100-00011110-00111111-11111111
+// CHECK-INST: andqv v31.16b, p7, z31.b
+// CHECK-ENCODING: [0xff,0x3f,0x1e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 041e3fff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/eorqv-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/eorqv-diagnostics.s
new file mode 100644
index 000000000000..9b812bc93f6f
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/eorqv-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+eorqv v0.2d, p11, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: eorqv v0.2d, p11, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector register
+
+eorqv v0.4h, p1, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: eorqv v0.4h, p1, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eorqv z1.s, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: eorqv z1.s, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+eorqv v0.8h, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: eorqv v0.8h, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/eorqv.s b/llvm/test/MC/AArch64/SVE2p1/eorqv.s
new file mode 100644
index 000000000000..98dcbc1c34b4
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/eorqv.s
@@ -0,0 +1,110 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+eorqv v0.8h, p0, z0.h // 00000100-01011101-00100000-00000000
+// CHECK-INST: eorqv v0.8h, p0, z0.h
+// CHECK-ENCODING: [0x00,0x20,0x5d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 045d2000 <unknown>
+
+eorqv v21.8h, p5, z10.h // 00000100-01011101-00110101-01010101
+// CHECK-INST: eorqv v21.8h, p5, z10.h
+// CHECK-ENCODING: [0x55,0x35,0x5d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 045d3555 <unknown>
+
+eorqv v23.8h, p3, z13.h // 00000100-01011101-00101101-10110111
+// CHECK-INST: eorqv v23.8h, p3, z13.h
+// CHECK-ENCODING: [0xb7,0x2d,0x5d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 045d2db7 <unknown>
+
+eorqv v31.8h, p7, z31.h // 00000100-01011101-00111111-11111111
+// CHECK-INST: eorqv v31.8h, p7, z31.h
+// CHECK-ENCODING: [0xff,0x3f,0x5d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 045d3fff <unknown>
+
+eorqv v0.4s, p0, z0.s // 00000100-10011101-00100000-00000000
+// CHECK-INST: eorqv v0.4s, p0, z0.s
+// CHECK-ENCODING: [0x00,0x20,0x9d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 049d2000 <unknown>
+
+eorqv v21.4s, p5, z10.s // 00000100-10011101-00110101-01010101
+// CHECK-INST: eorqv v21.4s, p5, z10.s
+// CHECK-ENCODING: [0x55,0x35,0x9d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 049d3555 <unknown>
+
+eorqv v23.4s, p3, z13.s // 00000100-10011101-00101101-10110111
+// CHECK-INST: eorqv v23.4s, p3, z13.s
+// CHECK-ENCODING: [0xb7,0x2d,0x9d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 049d2db7 <unknown>
+
+eorqv v31.4s, p7, z31.s // 00000100-10011101-00111111-11111111
+// CHECK-INST: eorqv v31.4s, p7, z31.s
+// CHECK-ENCODING: [0xff,0x3f,0x9d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 049d3fff <unknown>
+
+eorqv v0.2d, p0, z0.d // 00000100-11011101-00100000-00000000
+// CHECK-INST: eorqv v0.2d, p0, z0.d
+// CHECK-ENCODING: [0x00,0x20,0xdd,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04dd2000 <unknown>
+
+eorqv v21.2d, p5, z10.d // 00000100-11011101-00110101-01010101
+// CHECK-INST: eorqv v21.2d, p5, z10.d
+// CHECK-ENCODING: [0x55,0x35,0xdd,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04dd3555 <unknown>
+
+eorqv v23.2d, p3, z13.d // 00000100-11011101-00101101-10110111
+// CHECK-INST: eorqv v23.2d, p3, z13.d
+// CHECK-ENCODING: [0xb7,0x2d,0xdd,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04dd2db7 <unknown>
+
+eorqv v31.2d, p7, z31.d // 00000100-11011101-00111111-11111111
+// CHECK-INST: eorqv v31.2d, p7, z31.d
+// CHECK-ENCODING: [0xff,0x3f,0xdd,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04dd3fff <unknown>
+
+eorqv v0.16b, p0, z0.b // 00000100-00011101-00100000-00000000
+// CHECK-INST: eorqv v0.16b, p0, z0.b
+// CHECK-ENCODING: [0x00,0x20,0x1d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 041d2000 <unknown>
+
+eorqv v21.16b, p5, z10.b // 00000100-00011101-00110101-01010101
+// CHECK-INST: eorqv v21.16b, p5, z10.b
+// CHECK-ENCODING: [0x55,0x35,0x1d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 041d3555 <unknown>
+
+eorqv v23.16b, p3, z13.b // 00000100-00011101-00101101-10110111
+// CHECK-INST: eorqv v23.16b, p3, z13.b
+// CHECK-ENCODING: [0xb7,0x2d,0x1d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 041d2db7 <unknown>
+
+eorqv v31.16b, p7, z31.b // 00000100-00011101-00111111-11111111
+// CHECK-INST: eorqv v31.16b, p7, z31.b
+// CHECK-ENCODING: [0xff,0x3f,0x1d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 041d3fff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/orqv-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/orqv-diagnostics.s
new file mode 100644
index 000000000000..841150269d0b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/orqv-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+orqv v0.2d, p11, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: orqv v0.2d, p11, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector register
+
+orqv v0.4h, p1, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: orqv v0.4h, p1, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orqv z1.s, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: orqv z1.s, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+orqv v0.8h, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: orqv v0.8h, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/orqv.s b/llvm/test/MC/AArch64/SVE2p1/orqv.s
new file mode 100644
index 000000000000..a1640bcd7fb3
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/orqv.s
@@ -0,0 +1,110 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+orqv v0.8h, p0, z0.h // 00000100-01011100-00100000-00000000
+// CHECK-INST: orqv v0.8h, p0, z0.h
+// CHECK-ENCODING: [0x00,0x20,0x5c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 045c2000 <unknown>
+
+orqv v21.8h, p5, z10.h // 00000100-01011100-00110101-01010101
+// CHECK-INST: orqv v21.8h, p5, z10.h
+// CHECK-ENCODING: [0x55,0x35,0x5c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 045c3555 <unknown>
+
+orqv v23.8h, p3, z13.h // 00000100-01011100-00101101-10110111
+// CHECK-INST: orqv v23.8h, p3, z13.h
+// CHECK-ENCODING: [0xb7,0x2d,0x5c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 045c2db7 <unknown>
+
+orqv v31.8h, p7, z31.h // 00000100-01011100-00111111-11111111
+// CHECK-INST: orqv v31.8h, p7, z31.h
+// CHECK-ENCODING: [0xff,0x3f,0x5c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 045c3fff <unknown>
+
+orqv v0.4s, p0, z0.s // 00000100-10011100-00100000-00000000
+// CHECK-INST: orqv v0.4s, p0, z0.s
+// CHECK-ENCODING: [0x00,0x20,0x9c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 049c2000 <unknown>
+
+orqv v21.4s, p5, z10.s // 00000100-10011100-00110101-01010101
+// CHECK-INST: orqv v21.4s, p5, z10.s
+// CHECK-ENCODING: [0x55,0x35,0x9c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 049c3555 <unknown>
+
+orqv v23.4s, p3, z13.s // 00000100-10011100-00101101-10110111
+// CHECK-INST: orqv v23.4s, p3, z13.s
+// CHECK-ENCODING: [0xb7,0x2d,0x9c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 049c2db7 <unknown>
+
+orqv v31.4s, p7, z31.s // 00000100-10011100-00111111-11111111
+// CHECK-INST: orqv v31.4s, p7, z31.s
+// CHECK-ENCODING: [0xff,0x3f,0x9c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 049c3fff <unknown>
+
+orqv v0.2d, p0, z0.d // 00000100-11011100-00100000-00000000
+// CHECK-INST: orqv v0.2d, p0, z0.d
+// CHECK-ENCODING: [0x00,0x20,0xdc,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04dc2000 <unknown>
+
+orqv v21.2d, p5, z10.d // 00000100-11011100-00110101-01010101
+// CHECK-INST: orqv v21.2d, p5, z10.d
+// CHECK-ENCODING: [0x55,0x35,0xdc,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04dc3555 <unknown>
+
+orqv v23.2d, p3, z13.d // 00000100-11011100-00101101-10110111
+// CHECK-INST: orqv v23.2d, p3, z13.d
+// CHECK-ENCODING: [0xb7,0x2d,0xdc,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04dc2db7 <unknown>
+
+orqv v31.2d, p7, z31.d // 00000100-11011100-00111111-11111111
+// CHECK-INST: orqv v31.2d, p7, z31.d
+// CHECK-ENCODING: [0xff,0x3f,0xdc,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04dc3fff <unknown>
+
+orqv v0.16b, p0, z0.b // 00000100-00011100-00100000-00000000
+// CHECK-INST: orqv v0.16b, p0, z0.b
+// CHECK-ENCODING: [0x00,0x20,0x1c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 041c2000 <unknown>
+
+orqv v21.16b, p5, z10.b // 00000100-00011100-00110101-01010101
+// CHECK-INST: orqv v21.16b, p5, z10.b
+// CHECK-ENCODING: [0x55,0x35,0x1c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 041c3555 <unknown>
+
+orqv v23.16b, p3, z13.b // 00000100-00011100-00101101-10110111
+// CHECK-INST: orqv v23.16b, p3, z13.b
+// CHECK-ENCODING: [0xb7,0x2d,0x1c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 041c2db7 <unknown>
+
+orqv v31.16b, p7, z31.b // 00000100-00011100-00111111-11111111
+// CHECK-INST: orqv v31.16b, p7, z31.b
+// CHECK-ENCODING: [0xff,0x3f,0x1c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 041c3fff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/smaxqv-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/smaxqv-diagnostics.s
new file mode 100644
index 000000000000..822802cab2f1
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/smaxqv-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+smaxqv v0.2d, p11, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: smaxqv v0.2d, p11, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector register
+
+smaxqv v0.4h, p1, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smaxqv v0.4h, p1, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smaxqv z1.s, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smaxqv z1.s, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+smaxqv v0.8h, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smaxqv v0.8h, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/smaxqv.s b/llvm/test/MC/AArch64/SVE2p1/smaxqv.s
new file mode 100644
index 000000000000..844b9f90138b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/smaxqv.s
@@ -0,0 +1,110 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+smaxqv v0.8h, p0, z0.h // 00000100-01001100-00100000-00000000
+// CHECK-INST: smaxqv v0.8h, p0, z0.h
+// CHECK-ENCODING: [0x00,0x20,0x4c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 044c2000 <unknown>
+
+smaxqv v21.8h, p5, z10.h // 00000100-01001100-00110101-01010101
+// CHECK-INST: smaxqv v21.8h, p5, z10.h
+// CHECK-ENCODING: [0x55,0x35,0x4c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 044c3555 <unknown>
+
+smaxqv v23.8h, p3, z13.h // 00000100-01001100-00101101-10110111
+// CHECK-INST: smaxqv v23.8h, p3, z13.h
+// CHECK-ENCODING: [0xb7,0x2d,0x4c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 044c2db7 <unknown>
+
+smaxqv v31.8h, p7, z31.h // 00000100-01001100-00111111-11111111
+// CHECK-INST: smaxqv v31.8h, p7, z31.h
+// CHECK-ENCODING: [0xff,0x3f,0x4c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 044c3fff <unknown>
+
+smaxqv v0.4s, p0, z0.s // 00000100-10001100-00100000-00000000
+// CHECK-INST: smaxqv v0.4s, p0, z0.s
+// CHECK-ENCODING: [0x00,0x20,0x8c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 048c2000 <unknown>
+
+smaxqv v21.4s, p5, z10.s // 00000100-10001100-00110101-01010101
+// CHECK-INST: smaxqv v21.4s, p5, z10.s
+// CHECK-ENCODING: [0x55,0x35,0x8c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 048c3555 <unknown>
+
+smaxqv v23.4s, p3, z13.s // 00000100-10001100-00101101-10110111
+// CHECK-INST: smaxqv v23.4s, p3, z13.s
+// CHECK-ENCODING: [0xb7,0x2d,0x8c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 048c2db7 <unknown>
+
+smaxqv v31.4s, p7, z31.s // 00000100-10001100-00111111-11111111
+// CHECK-INST: smaxqv v31.4s, p7, z31.s
+// CHECK-ENCODING: [0xff,0x3f,0x8c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 048c3fff <unknown>
+
+smaxqv v0.2d, p0, z0.d // 00000100-11001100-00100000-00000000
+// CHECK-INST: smaxqv v0.2d, p0, z0.d
+// CHECK-ENCODING: [0x00,0x20,0xcc,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04cc2000 <unknown>
+
+smaxqv v21.2d, p5, z10.d // 00000100-11001100-00110101-01010101
+// CHECK-INST: smaxqv v21.2d, p5, z10.d
+// CHECK-ENCODING: [0x55,0x35,0xcc,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04cc3555 <unknown>
+
+smaxqv v23.2d, p3, z13.d // 00000100-11001100-00101101-10110111
+// CHECK-INST: smaxqv v23.2d, p3, z13.d
+// CHECK-ENCODING: [0xb7,0x2d,0xcc,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04cc2db7 <unknown>
+
+smaxqv v31.2d, p7, z31.d // 00000100-11001100-00111111-11111111
+// CHECK-INST: smaxqv v31.2d, p7, z31.d
+// CHECK-ENCODING: [0xff,0x3f,0xcc,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04cc3fff <unknown>
+
+smaxqv v0.16b, p0, z0.b // 00000100-00001100-00100000-00000000
+// CHECK-INST: smaxqv v0.16b, p0, z0.b
+// CHECK-ENCODING: [0x00,0x20,0x0c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 040c2000 <unknown>
+
+smaxqv v21.16b, p5, z10.b // 00000100-00001100-00110101-01010101
+// CHECK-INST: smaxqv v21.16b, p5, z10.b
+// CHECK-ENCODING: [0x55,0x35,0x0c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 040c3555 <unknown>
+
+smaxqv v23.16b, p3, z13.b // 00000100-00001100-00101101-10110111
+// CHECK-INST: smaxqv v23.16b, p3, z13.b
+// CHECK-ENCODING: [0xb7,0x2d,0x0c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 040c2db7 <unknown>
+
+smaxqv v31.16b, p7, z31.b // 00000100-00001100-00111111-11111111
+// CHECK-INST: smaxqv v31.16b, p7, z31.b
+// CHECK-ENCODING: [0xff,0x3f,0x0c,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 040c3fff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/sminqv-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/sminqv-diagnostics.s
new file mode 100644
index 000000000000..af2308755156
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/sminqv-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+sminqv v0.2d, p11, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: sminqv v0.2d, p11, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector register
+
+sminqv v0.4h, p1, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sminqv v0.4h, p1, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sminqv z1.s, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sminqv z1.s, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+sminqv v0.8h, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sminqv v0.8h, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/sminqv.s b/llvm/test/MC/AArch64/SVE2p1/sminqv.s
new file mode 100644
index 000000000000..180284991809
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/sminqv.s
@@ -0,0 +1,110 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+sminqv v0.8h, p0, z0.h // 00000100-01001110-00100000-00000000
+// CHECK-INST: sminqv v0.8h, p0, z0.h
+// CHECK-ENCODING: [0x00,0x20,0x4e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 044e2000 <unknown>
+
+sminqv v21.8h, p5, z10.h // 00000100-01001110-00110101-01010101
+// CHECK-INST: sminqv v21.8h, p5, z10.h
+// CHECK-ENCODING: [0x55,0x35,0x4e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 044e3555 <unknown>
+
+sminqv v23.8h, p3, z13.h // 00000100-01001110-00101101-10110111
+// CHECK-INST: sminqv v23.8h, p3, z13.h
+// CHECK-ENCODING: [0xb7,0x2d,0x4e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 044e2db7 <unknown>
+
+sminqv v31.8h, p7, z31.h // 00000100-01001110-00111111-11111111
+// CHECK-INST: sminqv v31.8h, p7, z31.h
+// CHECK-ENCODING: [0xff,0x3f,0x4e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 044e3fff <unknown>
+
+sminqv v0.4s, p0, z0.s // 00000100-10001110-00100000-00000000
+// CHECK-INST: sminqv v0.4s, p0, z0.s
+// CHECK-ENCODING: [0x00,0x20,0x8e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 048e2000 <unknown>
+
+sminqv v21.4s, p5, z10.s // 00000100-10001110-00110101-01010101
+// CHECK-INST: sminqv v21.4s, p5, z10.s
+// CHECK-ENCODING: [0x55,0x35,0x8e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 048e3555 <unknown>
+
+sminqv v23.4s, p3, z13.s // 00000100-10001110-00101101-10110111
+// CHECK-INST: sminqv v23.4s, p3, z13.s
+// CHECK-ENCODING: [0xb7,0x2d,0x8e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 048e2db7 <unknown>
+
+sminqv v31.4s, p7, z31.s // 00000100-10001110-00111111-11111111
+// CHECK-INST: sminqv v31.4s, p7, z31.s
+// CHECK-ENCODING: [0xff,0x3f,0x8e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 048e3fff <unknown>
+
+sminqv v0.2d, p0, z0.d // 00000100-11001110-00100000-00000000
+// CHECK-INST: sminqv v0.2d, p0, z0.d
+// CHECK-ENCODING: [0x00,0x20,0xce,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04ce2000 <unknown>
+
+sminqv v21.2d, p5, z10.d // 00000100-11001110-00110101-01010101
+// CHECK-INST: sminqv v21.2d, p5, z10.d
+// CHECK-ENCODING: [0x55,0x35,0xce,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04ce3555 <unknown>
+
+sminqv v23.2d, p3, z13.d // 00000100-11001110-00101101-10110111
+// CHECK-INST: sminqv v23.2d, p3, z13.d
+// CHECK-ENCODING: [0xb7,0x2d,0xce,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04ce2db7 <unknown>
+
+sminqv v31.2d, p7, z31.d // 00000100-11001110-00111111-11111111
+// CHECK-INST: sminqv v31.2d, p7, z31.d
+// CHECK-ENCODING: [0xff,0x3f,0xce,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04ce3fff <unknown>
+
+sminqv v0.16b, p0, z0.b // 00000100-00001110-00100000-00000000
+// CHECK-INST: sminqv v0.16b, p0, z0.b
+// CHECK-ENCODING: [0x00,0x20,0x0e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 040e2000 <unknown>
+
+sminqv v21.16b, p5, z10.b // 00000100-00001110-00110101-01010101
+// CHECK-INST: sminqv v21.16b, p5, z10.b
+// CHECK-ENCODING: [0x55,0x35,0x0e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 040e3555 <unknown>
+
+sminqv v23.16b, p3, z13.b // 00000100-00001110-00101101-10110111
+// CHECK-INST: sminqv v23.16b, p3, z13.b
+// CHECK-ENCODING: [0xb7,0x2d,0x0e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 040e2db7 <unknown>
+
+sminqv v31.16b, p7, z31.b // 00000100-00001110-00111111-11111111
+// CHECK-INST: sminqv v31.16b, p7, z31.b
+// CHECK-ENCODING: [0xff,0x3f,0x0e,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 040e3fff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/umaxqv-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/umaxqv-diagnostics.s
new file mode 100644
index 000000000000..a3aec1adba9a
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/umaxqv-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+umaxqv v0.2d, p11, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: umaxqv v0.2d, p11, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector register
+
+umaxqv v0.4h, p1, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umaxqv v0.4h, p1, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umaxqv z1.s, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umaxqv z1.s, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+umaxqv v0.8h, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umaxqv v0.8h, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/umaxqv.s b/llvm/test/MC/AArch64/SVE2p1/umaxqv.s
new file mode 100644
index 000000000000..d2fb918af19a
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/umaxqv.s
@@ -0,0 +1,110 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+umaxqv v0.8h, p0, z0.h // 00000100-01001101-00100000-00000000
+// CHECK-INST: umaxqv v0.8h, p0, z0.h
+// CHECK-ENCODING: [0x00,0x20,0x4d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 044d2000 <unknown>
+
+umaxqv v21.8h, p5, z10.h // 00000100-01001101-00110101-01010101
+// CHECK-INST: umaxqv v21.8h, p5, z10.h
+// CHECK-ENCODING: [0x55,0x35,0x4d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 044d3555 <unknown>
+
+umaxqv v23.8h, p3, z13.h // 00000100-01001101-00101101-10110111
+// CHECK-INST: umaxqv v23.8h, p3, z13.h
+// CHECK-ENCODING: [0xb7,0x2d,0x4d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 044d2db7 <unknown>
+
+umaxqv v31.8h, p7, z31.h // 00000100-01001101-00111111-11111111
+// CHECK-INST: umaxqv v31.8h, p7, z31.h
+// CHECK-ENCODING: [0xff,0x3f,0x4d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 044d3fff <unknown>
+
+umaxqv v0.4s, p0, z0.s // 00000100-10001101-00100000-00000000
+// CHECK-INST: umaxqv v0.4s, p0, z0.s
+// CHECK-ENCODING: [0x00,0x20,0x8d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 048d2000 <unknown>
+
+umaxqv v21.4s, p5, z10.s // 00000100-10001101-00110101-01010101
+// CHECK-INST: umaxqv v21.4s, p5, z10.s
+// CHECK-ENCODING: [0x55,0x35,0x8d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 048d3555 <unknown>
+
+umaxqv v23.4s, p3, z13.s // 00000100-10001101-00101101-10110111
+// CHECK-INST: umaxqv v23.4s, p3, z13.s
+// CHECK-ENCODING: [0xb7,0x2d,0x8d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 048d2db7 <unknown>
+
+umaxqv v31.4s, p7, z31.s // 00000100-10001101-00111111-11111111
+// CHECK-INST: umaxqv v31.4s, p7, z31.s
+// CHECK-ENCODING: [0xff,0x3f,0x8d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 048d3fff <unknown>
+
+umaxqv v0.2d, p0, z0.d // 00000100-11001101-00100000-00000000
+// CHECK-INST: umaxqv v0.2d, p0, z0.d
+// CHECK-ENCODING: [0x00,0x20,0xcd,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04cd2000 <unknown>
+
+umaxqv v21.2d, p5, z10.d // 00000100-11001101-00110101-01010101
+// CHECK-INST: umaxqv v21.2d, p5, z10.d
+// CHECK-ENCODING: [0x55,0x35,0xcd,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04cd3555 <unknown>
+
+umaxqv v23.2d, p3, z13.d // 00000100-11001101-00101101-10110111
+// CHECK-INST: umaxqv v23.2d, p3, z13.d
+// CHECK-ENCODING: [0xb7,0x2d,0xcd,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04cd2db7 <unknown>
+
+umaxqv v31.2d, p7, z31.d // 00000100-11001101-00111111-11111111
+// CHECK-INST: umaxqv v31.2d, p7, z31.d
+// CHECK-ENCODING: [0xff,0x3f,0xcd,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04cd3fff <unknown>
+
+umaxqv v0.16b, p0, z0.b // 00000100-00001101-00100000-00000000
+// CHECK-INST: umaxqv v0.16b, p0, z0.b
+// CHECK-ENCODING: [0x00,0x20,0x0d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 040d2000 <unknown>
+
+umaxqv v21.16b, p5, z10.b // 00000100-00001101-00110101-01010101
+// CHECK-INST: umaxqv v21.16b, p5, z10.b
+// CHECK-ENCODING: [0x55,0x35,0x0d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 040d3555 <unknown>
+
+umaxqv v23.16b, p3, z13.b // 00000100-00001101-00101101-10110111
+// CHECK-INST: umaxqv v23.16b, p3, z13.b
+// CHECK-ENCODING: [0xb7,0x2d,0x0d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 040d2db7 <unknown>
+
+umaxqv v31.16b, p7, z31.b // 00000100-00001101-00111111-11111111
+// CHECK-INST: umaxqv v31.16b, p7, z31.b
+// CHECK-ENCODING: [0xff,0x3f,0x0d,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 040d3fff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/uminqv-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/uminqv-diagnostics.s
new file mode 100644
index 000000000000..89429d26a784
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/uminqv-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+uminqv v0.2d, p11, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: uminqv v0.2d, p11, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector register
+
+uminqv v0.4h, p1, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uminqv v0.4h, p1, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uminqv z1.s, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uminqv z1.s, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+uminqv v0.8h, p1, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uminqv v0.8h, p1, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/uminqv.s b/llvm/test/MC/AArch64/SVE2p1/uminqv.s
new file mode 100644
index 000000000000..5bf2b948a3eb
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/uminqv.s
@@ -0,0 +1,110 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+uminqv v0.8h, p0, z0.h // 00000100-01001111-00100000-00000000
+// CHECK-INST: uminqv v0.8h, p0, z0.h
+// CHECK-ENCODING: [0x00,0x20,0x4f,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 044f2000 <unknown>
+
+uminqv v21.8h, p5, z10.h // 00000100-01001111-00110101-01010101
+// CHECK-INST: uminqv v21.8h, p5, z10.h
+// CHECK-ENCODING: [0x55,0x35,0x4f,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 044f3555 <unknown>
+
+uminqv v23.8h, p3, z13.h // 00000100-01001111-00101101-10110111
+// CHECK-INST: uminqv v23.8h, p3, z13.h
+// CHECK-ENCODING: [0xb7,0x2d,0x4f,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 044f2db7 <unknown>
+
+uminqv v31.8h, p7, z31.h // 00000100-01001111-00111111-11111111
+// CHECK-INST: uminqv v31.8h, p7, z31.h
+// CHECK-ENCODING: [0xff,0x3f,0x4f,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 044f3fff <unknown>
+
+uminqv v0.4s, p0, z0.s // 00000100-10001111-00100000-00000000
+// CHECK-INST: uminqv v0.4s, p0, z0.s
+// CHECK-ENCODING: [0x00,0x20,0x8f,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 048f2000 <unknown>
+
+uminqv v21.4s, p5, z10.s // 00000100-10001111-00110101-01010101
+// CHECK-INST: uminqv v21.4s, p5, z10.s
+// CHECK-ENCODING: [0x55,0x35,0x8f,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 048f3555 <unknown>
+
+uminqv v23.4s, p3, z13.s // 00000100-10001111-00101101-10110111
+// CHECK-INST: uminqv v23.4s, p3, z13.s
+// CHECK-ENCODING: [0xb7,0x2d,0x8f,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 048f2db7 <unknown>
+
+uminqv v31.4s, p7, z31.s // 00000100-10001111-00111111-11111111
+// CHECK-INST: uminqv v31.4s, p7, z31.s
+// CHECK-ENCODING: [0xff,0x3f,0x8f,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 048f3fff <unknown>
+
+uminqv v0.2d, p0, z0.d // 00000100-11001111-00100000-00000000
+// CHECK-INST: uminqv v0.2d, p0, z0.d
+// CHECK-ENCODING: [0x00,0x20,0xcf,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04cf2000 <unknown>
+
+uminqv v21.2d, p5, z10.d // 00000100-11001111-00110101-01010101
+// CHECK-INST: uminqv v21.2d, p5, z10.d
+// CHECK-ENCODING: [0x55,0x35,0xcf,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04cf3555 <unknown>
+
+uminqv v23.2d, p3, z13.d // 00000100-11001111-00101101-10110111
+// CHECK-INST: uminqv v23.2d, p3, z13.d
+// CHECK-ENCODING: [0xb7,0x2d,0xcf,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04cf2db7 <unknown>
+
+uminqv v31.2d, p7, z31.d // 00000100-11001111-00111111-11111111
+// CHECK-INST: uminqv v31.2d, p7, z31.d
+// CHECK-ENCODING: [0xff,0x3f,0xcf,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 04cf3fff <unknown>
+
+uminqv v0.16b, p0, z0.b // 00000100-00001111-00100000-00000000
+// CHECK-INST: uminqv v0.16b, p0, z0.b
+// CHECK-ENCODING: [0x00,0x20,0x0f,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 040f2000 <unknown>
+
+uminqv v21.16b, p5, z10.b // 00000100-00001111-00110101-01010101
+// CHECK-INST: uminqv v21.16b, p5, z10.b
+// CHECK-ENCODING: [0x55,0x35,0x0f,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 040f3555 <unknown>
+
+uminqv v23.16b, p3, z13.b // 00000100-00001111-00101101-10110111
+// CHECK-INST: uminqv v23.16b, p3, z13.b
+// CHECK-ENCODING: [0xb7,0x2d,0x0f,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 040f2db7 <unknown>
+
+uminqv v31.16b, p7, z31.b // 00000100-00001111-00111111-11111111
+// CHECK-INST: uminqv v31.16b, p7, z31.b
+// CHECK-ENCODING: [0xff,0x3f,0x0f,0x04]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 040f3fff <unknown>
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